Delay-Line Clock Deskewing for High-Speed IC Data Sampling
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Solution Overview
Problem
Integrated circuits face challenges in efficiently correcting clock skew due to the space inefficiency of phase-locked loops (PLLs) and delay-locked loops (DLLs) used for data signal synchronization, particularly at high data rates where systems are sensitive to timing variations.
Innovation Solution
A delay line controlled by a state machine, in conjunction with existing chip architecture, such as the Serial-In Parallel-Out (SIPO) block, is used to sample incoming data signals and adjust the clock signal to align with the data valid window, eliminating skew without the need for complex PLLs or DLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loops (PLLs) or delay-locked loops (DLLs) are used to correct clock skew, then timing synchronization is improved, but chip space efficiency deteriorates
Solution Approach 1:
The patent extracts the essential function of PLL/DLL (timing synchronization) and implements it using a simplified delay line mechanism controlled by a state machine, removing the complex oscillator and feedback components while retaining the core deskewing capability
Solution Approach 2:
The patent creates a simplified copy of the PLL/DLL functionality using a delay line that replicates the timing adjustment capability without requiring the full complexity of traditional loop-based synchronization circuits
2Reliability
If serial transmission is used to reduce skew, then timing stability is improved, but data transmission speed deteriorates
Solution Approach 1:
The patent implements a dynamic delay line that can adjust its delay characteristics based on detected timing skew, allowing the system to optimize for both timing stability and transmission speed by adapting to actual signal conditions
Solution Approach 2:
The patent changes the delay parameter of the delay line dynamically to compensate for timing skew, enabling the system to maintain timing stability while supporting higher transmission speeds by adjusting the delay to match actual signal arrival times
Data Source
AI summary
The present invention discloses a method and apparatus for addressing the issue of clock skew in a data signal while making efficient use of space on an integrated chip (IC) by utilizing a physical delay line controlled by a state machine in conjunction with pre-requisite chip architecture. The pre-requisite chip architecture samples the incoming data signal in response to a clocking signal input from the physical delay line; the physical delay line responds to commands from the state machine to increment the delay of the physical delay line to produce samples which describe the incoming data signal and delineate its data valid window.