Delay-Line Clock Frequency Doubling With Stable Duty Cycle
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Solution Overview
Problem
Existing semiconductor integrated circuit signal frequency change circuits suffer from duty cycle errors and increased current consumption due to fluctuations in the delay device and the operation of oscillators, leading to inefficiencies and increased circuit area.
Innovation Solution
A signal frequency change circuit that includes a delay line, a detector, a controller, and a multiplexer to generate a frequency change clock signal with a stable duty cycle by delaying the clock signal, detecting specific phases, and selectively outputting pre-frequency change clock signals to achieve a frequency twice that of the input clock signal while minimizing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a delay device is used to generate a frequency change clock signal, then the frequency can be doubled, but the duty cycle significantly fluctuates according to the delay device, increasing the probability of generating a duty cycle error
Solution Approach 1:
The delay line is divided into multiple delay units, each contributing a portion of the total delay. This segmentation allows for more precise control of the delay amount, reducing duty cycle fluctuations while achieving frequency multiplication.
Solution Approach 2:
A detector is introduced to detect the duty cycle of the generated clock signal and provide feedback to the controller. The controller adjusts the delay control signal based on this feedback to maintain a stable duty cycle, thereby resolving the duty cycle error issue.
2Speed
If an oscillator is used to generate a high frequency oscillation signal, then a suitable clock signal for testing can be provided, but the current consumption is increased
Solution Approach 1:
Instead of using a continuous oscillator, the circuit uses periodic switching of delay units controlled by the clock signal edges. This periodic action achieves frequency multiplication without the continuous power consumption of an oscillator.
Solution Approach 2:
The circuit uses the input clock signal itself to control the switching of delay units, eliminating the need for an external oscillator. The clock signal serves dual purposes: as the input signal and as the control signal for frequency multiplication.
3Speed
If the number of bits of the output signal of the counter is increased to achieve higher frequency multiplication, then the frequency can be increased, but the circuit area is increased
Solution Approach 1:
The frequency multiplication is achieved by segmenting the delay line into multiple units and selectively activating them, rather than using a counter with multiple bits. This segmentation approach achieves the same frequency multiplication effect with reduced circuit area.
Solution Approach 2:
The counter component is completely removed from the circuit. Instead of using a counter to achieve frequency multiplication, the patent extracts this function and implements it through the delay line and multiplexer combination, significantly reducing circuit area.
Data Source
AI summary
A signal frequency change circuit is presented. The signal frequency change circuit includes a delay line, a detector, a controller, a multiplexer, and an output unit. The delay line delays a clock signal by a first delay time corresponding to a delay control signal to generate a delay signal and delays the clock signal by a second delay time shorter than a first delay time to generate a pre-frequency change clock signal. The detector generates a phase locked completion signal. The controller sequentially shifts the delay control signal and a multiplexing control signal. The multiplexer selects and outputs one of the pre-frequency change clock signals. The output unit generates a frequency change clock signal.