Adaptive Clock Modulation Using Delay Lines for Voltage Droops
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Solution Overview
Problem
Conventional methods for mitigating voltage droops in integrated circuits lead to increased power consumption and performance loss due to inefficiencies in predicting workload changes and reactive measures, such as charge injection, digital linear voltage regulation, and clock squashing, which fail to effectively manage varying degrees of voltage droops.
Innovation Solution
An adaptive clock modulation (ACM) system that includes a delay circuit, frequency clamp, and squash controller to dynamically adjust clock frequencies based on detected voltage thresholds, preventing setup violations and optimizing power and performance metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard approaches (charge injection, digital linear voltage regulation, clock squashing) are used to mitigate voltage droop, then voltage stability is improved, but power consumption increases and performance decreases
Solution Approach 1:
The patent dynamically changes the clock frequency parameter based on detected voltage droop conditions. The ACM circuit monitors supply voltage and adjusts clock frequency in real-time, reducing frequency during voltage droop events to prevent setup violations while avoiding the continuous power consumption of traditional mitigation approaches. This parameter adaptation allows the system to maintain voltage stability only when necessary, rather than continuously consuming power.
Solution Approach 2:
The system uses the voltage droop detection capability inherent in the clocking circuitry itself to trigger frequency adjustment. The ACM circuit leverages existing voltage monitoring mechanisms and uses the clock signal's own characteristics (through delay elements and feedback) to detect and respond to voltage conditions, eliminating the need for separate power-intensive regulation circuits.
2Productivity
If proactive scheduling is used to predict workload changes, then performance is improved, but false positives and false negatives occur leading to unnecessary slowdowns
Solution Approach 1:
The ACM circuit implements direct feedback from voltage monitoring to clock frequency control. Instead of predicting future workload conditions, the system continuously monitors actual supply voltage conditions and immediately adjusts clock frequency in response to detected voltage droop events. This feedback mechanism eliminates false positives and false negatives by reacting only to actual voltage conditions that would cause setup violations, rather than relying on predictive algorithms.
Solution Approach 2:
The delay circuit elements in the ACM path provide preliminary timing adjustment before the clock signal reaches functional units. By pre-adjusting clock timing based on detected voltage conditions, the system prevents setup violations before they occur, rather than needing to predict or react after the fact.
3Reliability
If clock frequency is continuously adjusted to prevent setup violations, then reliability is improved, but power consumption increases due to unnecessary frequency adjustments
Solution Approach 1:
The ACM circuit applies clock frequency adjustment only partially - specifically during detected voltage droop events that would cause setup violations. Rather than continuously adjusting frequency or using excessive mitigation, the system applies just enough frequency reduction to prevent violations during actual voltage problems, avoiding unnecessary power consumption during normal operating conditions.
Data Source
AI summary
Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.