Controlled Delay Line Phase Detection for Multi-Phase Clock Locking
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Solution Overview
Problem
Conventional multi-phase clock generation circuits face challenges in generating high-frequency clocks without incurring significant power consumption and physical space penalties, particularly at millimeter wave frequencies, due to the need for large strings of delay circuits and limited precision in error detection at high frequencies.
Innovation Solution
A multi-phase clock generator employing a controlled delay line with phase error detection between multiple delay circuit outputs, using a phase error detector circuit to correct phase errors and reduce direct current offsets, allowing for the generation of high-frequency clocks with a small footprint and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional multi-phase clock generation circuits use frequency dividers or phase interpolation to generate high-frequency clocks, then the clock frequency can be increased, but power consumption increases and manufacturing precision becomes insufficient
Solution Approach 1:
The patent replaces traditional mechanical delay circuits with a digitally controlled delay line that uses binary-weighted delay elements. This substitution allows for programmable delay control with fewer physical components, reducing power consumption while maintaining the ability to generate high-frequency multi-phase clocks. The digital control mechanism replaces analog delay adjustment, improving both power efficiency and precision.
Solution Approach 2:
The delay line is segmented into multiple binary-weighted delay elements that can be independently controlled. This segmentation allows for fine-grained phase adjustment with fewer total components compared to traditional approaches. Each segment contributes a specific delay amount (2^0, 2^1, 2^2, etc.), enabling precise phase control with reduced overall circuit complexity and power consumption.
2Measurement precision
If conventional multi-phase clock generation circuits use large strings of delay circuits to detect phase errors at high frequencies, then error detection capability is improved, but device area increases
Solution Approach 1:
The patent transitions from spatial expansion (adding more delay circuits in sequence) to temporal/digital dimension by using a digitally controlled delay line. The binary-weighted delay elements can be controlled through digital signals to achieve the same phase error detection precision that would otherwise require a much longer physical chain of delay circuits. This dimensional shift reduces device area while maintaining measurement precision.
Solution Approach 2:
The patent changes the control parameter from analog delay adjustment to digital control codes. By using binary-weighted delay elements controlled by digital signals, the system achieves high phase error detection precision with fewer physical components. The digital control mechanism allows for precise adjustment of delay parameters without requiring proportional increases in device area.
3Speed
If conventional multi-phase clock generation circuits use phase locked loops with frequency dividers to generate high-frequency clocks, then clock frequency can be increased, but power consumption and device complexity increase
Solution Approach 1:
The patent extracts and eliminates the frequency divider component from the traditional PLL architecture. By using a digitally controlled delay line that can directly generate high-frequency multi-phase clocks without requiring frequency division, the design simplifies the overall circuit structure. The delay line is configured to produce the desired output frequency directly, removing the need for separate frequency division stages and reducing overall device complexity.
Data Source
AI summary
Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled delay line and a phase error detector circuit. Tap nodes are provided from outputs of one or more delay circuits in the controlled delay line. To detect and correct for phase errors in the controlled delay line, a phase detection circuit is provided that includes at least two phase detectors each configured to measure a phase offset error between tap nodes from the delay circuit(s) in the controlled delay line. These phase errors are then combined to create an error correction signal, which is used to control the delay of the delay circuit(s) in the controlled delay line to lock the phase of the output of the final delay circuit to an input reference clock signal.