Delay-Line Clock Multiplier for Low-Power Phase Control
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Solution Overview
Problem
Existing clock signal frequency adjustment techniques in digital circuits are prone to inaccuracies due to temperature and voltage fluctuations, and conventional frequency multipliers have high current and power requirements, making them unsuitable for compact and efficient use in devices like mobile telephone handsets.
Innovation Solution
A frequency multiplier circuit using serially connected delay elements and a phase detector to generate multiple clock signals with controlled phase shifts, enabling low-power operation and compact design suitable for mobile devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional frequency multipliers are used to generate clock signals, then the frequency requirement is met, but the current and power requirements become excessively high
Solution Approach 1:
The frequency multiplication function is segmented into multiple delay elements arranged in a ring structure, where each element contributes a portion of the total phase shift. This segmentation allows the system to achieve frequency multiplication through cumulative phase shifts rather than requiring a single high-power frequency multiplier component.
Solution Approach 2:
The patent replaces conventional frequency multiplier circuits with a digital delay element-based ring oscillator system. This substitution uses digital logic elements with controlled delay characteristics to generate the desired frequency multiplication effect, thereby reducing power consumption and current requirements while maintaining frequency accuracy.
2Speed
If conventional frequency multipliers are used, then frequency multiplication is achieved, but the circuit size becomes large making compact placement impractical
Solution Approach 1:
The delay elements are arranged in a compact ring configuration where the output of each element feeds into the next, creating a nested circular structure. This nesting allows the frequency multiplication function to be achieved within a minimal footprint, as the signal path is efficiently routed through the ring without requiring additional space for separate components.
Solution Approach 2:
Multiple functions are merged into the ring oscillator structure: frequency multiplication, phase shifting, and signal distribution are all achieved through the same compact arrangement of delay elements, eliminating the need for separate circuits and reducing overall device area.
3Adaptability or versatility
If existing clock signal frequency adjustment techniques are used, then frequency change is possible, but the duty cycle becomes inaccurate and difficult to control due to temperature and voltage fluctuations
Solution Approach 1:
The phase detector continuously monitors the phase relationship between the input clock signal and the delayed signal from the ring oscillator. This feedback mechanism allows the system to detect and correct for temperature and voltage-induced variations, maintaining accurate duty cycle control while enabling frequency adjustment through the selectable delay elements.
Solution Approach 2:
The system dynamically selects different delay elements based on the desired output frequency and operating conditions. By making the delay configuration adjustable rather than fixed, the system can adapt to temperature and voltage changes while maintaining precise duty cycle control through the feedback from the phase detector.
Data Source
AI summary
Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled.