Delay-Line Phase Measurement for Low-Frequency Clock Ratios
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Solution Overview
Problem
Existing phase measurement technologies face challenges in accurately measuring phase differences between clock signals with integer and fractional ratios, especially when the common frequency is low, leading to instability and complexity in digital implementations, and require significant power and calibration processes.
Innovation Solution
A phase measurement circuitry using a delay line with delay units configured to provide a propagation delay, sampling the delay line at successive times to record signal edge positions and determine phase angles per delay unit, allowing for accurate phase error detection between clock signals without the need for extensive calibration or complex circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital phase measurement is implemented using conventional methods, then phase difference can be measured, but measurement precision deteriorates when clock signals have integer ratios with low common frequency
Solution Approach 1:
The patent introduces a delay line as an intermediary component between the two clock signals. The delay line converts phase difference measurement into time difference of arrival (TDoA) measurement by propagating one clock signal through the delay line and comparing it with the other clock signal. This intermediary approach enables accurate phase measurement even when clocks have integer ratios with low common frequency, resolving the contradiction between measurement precision and reliability.
2Measurement precision
If calibration processes are implemented to improve measurement accuracy, then phase measurement precision improves, but device complexity and power consumption increase
Solution Approach 1:
The delay line is designed to be self-calibrating by using the clock signals themselves for measurement. The system automatically determines phase difference by measuring the time difference of arrival without requiring external calibration equipment or complex calibration procedures. This self-service approach maintains high measurement precision while eliminating the need for extensive calibration circuitry and procedures.
3Measurement precision
If higher sampling rates are used to improve phase detection accuracy, then measurement precision improves, but power consumption increases
Solution Approach 1:
The patent changes the measurement parameter from direct phase comparison to time difference of arrival (TDoA) measurement. By measuring the time it takes for a signal to propagate through the delay line and compare it with the reference clock, the system achieves high phase detection accuracy without requiring continuous high-speed sampling. This parameter change enables accurate measurement at lower sampling rates, thereby reducing power consumption.
Data Source
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AI summary
The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.