Delay-Line Clock Phase Generation for Wide-Range Phase Accuracy
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Solution Overview
Problem
Existing systems for clock phase generation struggle to accurately adjust and synchronize local clock phases over a wide range of frequencies, particularly at high data rates, leading to complexity and accuracy issues in phase blending circuitry.
Innovation Solution
A variable phase signal generator using a delay line, phase detector, charge pump, and digital-to-analog converter to create a phase offset signal, allowing for precise control of the phase difference between input and output signals, enabling accurate phase adjustment independent of data rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If prior art phase blender circuitry uses ratio processing between I and Q signals to sweep phase, then phase adjustment is achieved, but circuit complexity increases and accuracy deteriorates at high frequencies and wide frequency bands
Solution Approach 1:
The patent changes the fundamental parameter from ratio processing to time-delay processing. Instead of varying the ratio between I and Q signals, the system varies the time delay applied to the I signal relative to the Q signal. This parameter change simplifies the circuit architecture while maintaining phase sweep capability across wide frequency bands and high data rates.
Solution Approach 2:
The patent replaces the complex analog ratio processing mechanism with a simpler time-domain delay mechanism. By substituting the mechanical/analog ratio blending approach with a digital delay-based approach, the system achieves reduced circuit complexity while improving accuracy at high frequencies.
2Adaptability or versatility
If prior art systems operate over a 10× range of data rates from 2-3 Gb/s to 28 GB/s, then versatility is improved, but phase accuracy deteriorates due to complicated ratio processing
Solution Approach 1:
The patent creates a universal phase adjustment mechanism that functions accurately across all data rates from 2-3 Gb/s to 28 GB/s. The time-delay based approach serves multiple functions: it provides accurate phase control at low data rates, maintains accuracy at high data rates, and works across the entire 10× frequency range without requiring different circuit implementations.
Solution Approach 2:
By changing from frequency-dependent ratio processing to time-delay processing, the system achieves parameter independence. The time delay can be precisely controlled and scaled to work accurately across the entire data rate range, making the phase adjustment mechanism universally applicable regardless of operating frequency.
3Reliability
If prior art phase blending is used to lock local clock to data signal phase, then synchronization is achieved, but the system becomes complicated and inaccurate at high frequencies
Solution Approach 1:
The patent replaces the complex analog phase blending mechanism with a simpler time-delay based synchronization system. The delay line provides direct time alignment between the local clock and data signal, eliminating the need for complex ratio processing and blending circuitry while maintaining synchronization reliability at high frequencies.
Solution Approach 2:
The patent introduces a delay line as an intermediary element between the local clock and the data signal. This intermediary component directly controls the phase relationship through time delay, simplifying the synchronization mechanism while improving accuracy at high frequencies by eliminating complex blending operations.
Data Source
AI summary
A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.