Digital Delay Line Coding for Accurate DLL Clock Phase Control
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Solution Overview
Problem
Increasing internal clock frequency in electronic devices for higher data transfer rates is hindered by harmonic locking and phase delay mismatching due to process variations, making it difficult to generate clocks with accurate phase delay and uniform duty ratio.
Innovation Solution
A digital delay line with a code converter that uses a discontinuous thermometer code to select delay cells, comprising a group bit decoder, shared bit decoder, and code output cell array, to generate a delay clock with reduced area consumption and improved phase accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If internal clock frequency is increased to improve data transfer rate, then productivity is improved, but harmonic locking occurs during DLL locking operation and phase delay accuracy deteriorates
Solution Approach 1:
The delay line is divided into multiple delay cells (e.g., 256 delay cells) that can be independently selected through the discontinuous thermometer code. This segmentation allows precise control of phase delay by selectively activating specific delay cells, thereby achieving accurate phase delay even at high clock frequencies without harmonic locking issues.
2Device complexity
If manufacturing process is miniaturized to improve integration, then device complexity is reduced, but process variations cause delay line phase delay mismatching and duty ratio uniformity deteriorates
Solution Approach 1:
Each delay cell in the delay line is designed with identical local structure and characteristics. The discontinuous thermometer code selectively activates specific delay cells based on the desired phase delay, ensuring that each selected cell contributes uniformly to the overall delay. This local uniformity compensates for process variations and maintains duty ratio uniformity despite miniaturization.
Solution Approach 2:
The invention changes the control code format from binary to discontinuous thermometer code, which directly maps to delay cell selection. This parameter change in the control mechanism enables precise selection of delay cells while maintaining uniform delay characteristics across process variations, as each delay cell is designed to provide consistent delay when activated.
3Device complexity
If conventional binary control code is used for delay cell selection, then device complexity is low, but area consumption is large and phase delay accuracy is insufficient
Solution Approach 1:
The discontinuous thermometer code uses a periodic pattern of active bits that directly corresponds to the cumulative activation of delay cells. Instead of binary weighting, each bit position represents a specific group of delay cells, creating a periodic selection pattern that reduces the number of logic gates required while maintaining precise phase delay control.
Data Source
AI summary
A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.