Variable Delay Line Clock Synchronization With Rotating Registers
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Solution Overview
Problem
Modern chip designs face challenges in synchronizing clocks across different parts of the chip due to variable delay lines, leading to inconsistent clock stopping during debugging, where precise cycle synchronization is required to capture binary values accurately.
Innovation Solution
The implementation of rotating registers and multiplexers that synchronize reset signals with input and output clocks, ensuring data synchronization across the chip by controlling multiplexers with flip-flops, allowing for deterministic cycle delay and precise clock stopping through a JTAG interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable delay lines are used to introduce delay as needed, then adaptability is improved, but clock synchronization precision deteriorates
Solution Approach 1:
A mediator circuit is introduced that receives the reset signal and generates synchronized reset signals for both the input clock rotating register and output clock rotating register. This mediator ensures that despite the variable delay lines causing different clock phases at different locations, the reset operations occur at corresponding clock cycles, thereby maintaining synchronization precision while preserving the adaptability of variable delay lines.
2Reliability
If reset signals are sent to initialize rotating registers, then reliability is improved, but clock cycle consistency deteriorates
Solution Approach 1:
The system employs feedback mechanisms where the reset signal propagation is monitored and adjusted to ensure it reaches both rotating registers at the appropriate clock cycles. The feedback ensures that the reset operation maintains reliability while preserving clock cycle consistency by adjusting the timing based on the actual clock phase at each register location.
3Measurement precision
If rotating registers and multiplexers are used for data synchronization, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The data synchronization function is segmented into distinct components: input clock rotating register, output clock rotating register, multiplexers, and a mediator circuit. Each segment handles a specific aspect of the synchronization task, which improves measurement precision through dedicated functionality while managing complexity by modularizing the circuit structure.
Solution Approach 2:
The rotating registers and multiplexers are designed to perform multiple functions: data storage, data routing, and clock synchronization. This multi-functionality reduces the need for separate dedicated circuits, thereby improving synchronization precision without proportionally increasing device complexity.
Data Source
AI summary
In an embodiment, a method includes initializing an input clock rotating register by sending a reset signal synchronized to an input clock signal and initializing an output clock rotating register by sending the reset signal synchronized to an output clock signal. The method further providing a data input synchronized to the output clock to a plurality of mux-flops. The output clock rotating register activates one of the plurality of mux-flops to receive the data input. The method further includes forwarding the data input via the one of the plurality of mux-flops to a multiplexer. The multiplexer has a selection input of the input clock rotating register. The method further includes selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.