Delay Line Circuit Expands Data Window for Skew
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In on-chip environments where source synchronous data and clock signals are transmitted over long distances, skew between the clock and data signals makes it difficult to reliably capture valid data at the center of the data window, especially when using SDR (single data rate) protocols, as the sample clock may jitter relative to the remote clock.
Innovation Solution
A circuit design incorporating a first delay line for shifting the clock and a second delay line for shifting data, along with a logic block that identifies and forwards the predetermined section of the data window without memory elements or feedback lines, allowing for the expansion of the valid data window by shifting and aligning the clock and data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If source synchronous data and clock signals are transmitted over long distances on-chip, then data transmission capability is improved, but skew between clock and data signals increases making reliable capture difficult
Solution Approach 1:
The patent segments the clock and data signals into multiple delayed versions using delay lines. By creating multiple time-shifted copies of the clock and data signals, the system can sample across multiple time points, effectively segmenting the single critical sampling point into multiple opportunities for valid data capture.
Solution Approach 2:
The patent introduces dynamic delay adjustment mechanisms that allow the delay line parameters to be tuned based on actual skew conditions. This dynamic adaptation enables the system to optimize sampling timing in response to varying transmission conditions, making the capture process reliable despite long-distance skew.
2Measurement precision
If the sample clock is synchronized to the remote clock, then data sampling timing is improved, but clock jitter reduces the ability to reliably capture data at the center of the data window
Solution Approach 1:
The patent performs preliminary actions by generating multiple delayed clock and data signals before the actual sampling occurs. These pre-delayed signals are prepared in advance through the delay lines, creating a bank of time-shifted signals that cover a range of possible valid sampling points, ensuring that jitter does not cause complete sampling failure.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors which delayed signal combinations produce valid data captures and uses this information to adjust delay line parameters. This feedback loop allows the system to adapt to jitter conditions by learning which timing offsets yield successful data capture.
3Manufacturing precision
If strict setup and hold time requirements are enforced for storage elements, then data capture accuracy is improved, but the design becomes more complex and less robust to timing variations
Solution Approach 1:
The patent changes the timing parameters of the system by introducing variable delay lines that can adjust their delay characteristics. This parameter adjustment allows the system to accommodate timing variations without requiring strict fixed setup and hold times, thereby reducing design complexity while maintaining capture accuracy through adaptive timing.
Data Source
AI summary
In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.