Digitally Tuned Delay Line Circuit for Low-Jitter DDR Timing
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Solution Overview
Problem
High-speed DDR systems face increased clock jitter due to inconsistent delay step variations in delay lines, which introduce noise into the output signal, particularly with step delays in the 6-8 picosecond range.
Innovation Solution
A delay line circuit with a digitally controlled delay line controller and phase interpolator, comprising multiple delay units and a phase interpolator, which allows for tunable delays across a wide frequency range and reduces step delay variations by fine-tuning the phase difference between input and output signals using a speed control unit and process sensing circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay lines are used to provide linear steps for signal timing adjustment, then signal timing control is achieved, but inconsistent delay step variations increase clock jitter
Solution Approach 1:
The patent changes the delay step parameter from fixed (6-8 ps) to variable by dynamically adjusting the operating conditions of delay units. The control logic modifies delay characteristics based on detected signal edge transitions, transforming a static parameter into a dynamic one that adapts to reduce jitter while maintaining timing control precision
Solution Approach 2:
The patent implements feedback by detecting the actual delay step variations and using this information to adjust subsequent delay operations. The system monitors the output signals from delay units and feeds this information back to the control logic, which then compensates for inconsistent delay steps by adjusting control signals to minimize clock jitter
2Measurement precision
If step delay is reduced to improve timing precision, then signal alignment improves, but delay variation becomes more significant
Solution Approach 1:
The patent makes the delay units dynamic by allowing their delay characteristics to change based on control signals. Instead of fixed delay steps, the system dynamically adjusts the delay amount by modifying the operating state of delay units (e.g., changing transistor gate voltages), enabling the delay to adapt in real-time to maintain consistency despite small step sizes
Solution Approach 2:
The patent performs preliminary calibration and adjustment of delay units before actual operation. The control logic pre-adjusts the delay characteristics based on expected operating conditions and detected variations, compensating for potential inconsistencies before they affect timing precision. This proactive adjustment prevents delay variation from degrading timing accuracy
Data Source
AI summary
A delay line circuit includes: a coarse-tuning arrangement, including delay units; and a fine-tuning arrangement including at least three serially-connected inverters. The coarse-tuning arrangement is configured to receive an input signal and coarsely-tune the input signal, the coarsely-tuning including transferring the input signal through a selected number of the delay units and thereby producing a first output signal. The fine-tuning arrangement is configured to receive the first output signal, finely-tune the first output signal, and produce a second output signal, the finely-tuning including selectively connecting a speed control unit to a node between a corresponding pair of the at least three serially-connected inverters.