Delay-Line Digital Timer for Sub-Sample Timing Accuracy
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Solution Overview
Problem
Digital timers suffer from inherent timing errors due to synchronization issues, making it difficult to achieve high accuracy and long absolute timer delays, especially when the desired delay is a fraction of a switching period of a power converter.
Innovation Solution
A digital timer circuit that uses a delay line with multiple units connected in series to determine and reproduce a time offset interval between a clock signal and a trigger signal, allowing for a counter to generate a response signal independent of the clock signal's period, thereby reducing synchronization errors. This circuit includes a multiplexer for reusing the delay line and reducing circuit elements, and uses two timer circuits with different polarities to ensure accurate measurement across all phase constellations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a digital timer uses a clock-based synchronous counter, then the timer can be implemented without additional trimming circuits and can achieve arbitrary long delays, but the timer suffers from inherent timing errors due to synchronization with the clock signal
Solution Approach 1:
The timer operation is divided into distinct phases: a capture phase where the asynchronous trigger edge is detected and the time offset is measured, and a count phase where the predetermined number of clock cycles is counted. This segmentation allows the system to separate the asynchronous trigger detection from the synchronous counting operation, thereby reducing synchronization errors while maintaining ease of manufacture.
Solution Approach 2:
The system performs preliminary measurement of the time offset interval between the clock edge and the asynchronous trigger edge during the capture phase before the main counting operation begins. This preliminary action allows the system to compensate for synchronization errors in advance, improving timing precision without requiring additional trimming circuits.
2Ease of operation
If an analog timer is used to achieve asynchronous triggering and immediate response, then the system can respond immediately to trigger events independent of clock cycles, but it becomes difficult to implement long and accurate timers requiring substantial trimming to counteract PVT variation effects
Solution Approach 1:
The system introduces an intermediary delay line that captures the asynchronous trigger edge and holds it until the next clock edge. This intermediary structure allows the system to accept asynchronous triggers while still operating in a synchronous framework, achieving immediate response capability without requiring substantial trimming circuits to counteract PVT variations.
Solution Approach 2:
The system changes the operational parameters by using a digital counter that can count an arbitrary number of clock cycles, replacing the continuous time measurement of analog timers. This parameter change allows long delay times to be achieved through software configuration rather than hardware trimming, reducing device complexity while maintaining asynchronous triggering capability.
3Measurement precision
If the desired delay is defined as a fraction of a switching period of a power converter, then the timer can be precisely synchronized with the power converter, but legacy timer implementations struggle to achieve this precision
Solution Approach 1:
The system uses feedback by continuously monitoring the relationship between the trigger signal and clock signal edges, measuring the time offset, and adjusting the timing accordingly. This feedback mechanism enables precise synchronization with the power converter switching period, allowing delay times to be accurately defined as fractions of the switching period while maintaining manageable device complexity.
Data Source
AI summary
The present document relates to a timer which is counter-based and uses an asynchronous circuitry to improve the accuracy between the available clock cycles. In particular, a timer is presented which may comprise a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal. The first timer circuit may be configured to determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal.