Digital Delay Line Calibration for Duty Cycle Distortion
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Solution Overview
Problem
Existing digital delay line calibration methods for high bandwidth memory interfaces are inaccurate due to duty cycle distortion, leading to reduced operating speeds and increased power consumption, as they typically measure only one phase of the clock signal.
Innovation Solution
A method that measures both phases of the clock signal to generate a more accurate calibration value for digital delay lines, compensating for duty cycle distortion and allowing higher-speed operation while reducing power consumption and die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital delay line calibration measures only one phase of the clock signal, then the calibration process is simple and fast, but the calibration accuracy deteriorates due to duty cycle distortion
Solution Approach 1:
The calibration process is segmented into two independent measurements: one for the first phase of the clock signal and another for the second phase. Each phase is calibrated separately through its own delay line, and the results are combined to produce the final calibration value. This segmentation allows accurate compensation for duty cycle distortion while keeping each individual measurement simple and fast.
Solution Approach 2:
The calibration results from both phase measurements are merged through an averaging process to generate the final calibration value. This combining of measurements from both phases eliminates the error introduced by duty cycle distortion, as the inaccuracies in one phase are compensated by the other, achieving high calibration accuracy without requiring complex correction algorithms.
2Speed
If digital delay lines are calibrated inaccurately due to duty cycle distortion, then power consumption and die area can be reduced, but operating speed must be reduced to maintain reliability
Solution Approach 1:
The system performs preliminary calibration of the delay lines using the accurate two-phase measurement method before high-speed operation begins. This preliminary action ensures that the delay lines are precisely calibrated to compensate for duty cycle distortion, enabling the system to operate at high speeds without requiring excessive power margin or area overhead for error correction during operation.
3Reliability
If digital delay lines are calibrated inaccurately due to duty cycle distortion, then device complexity can be reduced, but timing margin and reliability deteriorate
Solution Approach 1:
The calibration methodology is segmented into separate first-phase and second-phase measurements, each processed through independent delay line calibration paths. This segmentation isolates the complexity of handling duty cycle distortion into manageable, repeatable measurement steps, maintaining timing margin and reliability without requiring overly complex integrated correction systems.
Solution Approach 2:
The system changes the measurement parameter from a single-phase timing measurement to dual-phase timing measurements. By measuring both the first phase and second phase of the clock signal and averaging the results, the system achieves accurate compensation for duty cycle distortion, ensuring sufficient timing margin and reliability while keeping the implementation relatively simple.
Data Source
AI summary
Embodiments include a memory device with an improved calibration circuit. Memory device input/output pins include delay lines for adjusting the delay in each memory input/output signal path. The delay adjustment circuitry includes digital delay lines for adjusting this delay. Further, each digital delay line is calibrated via a digital delay line locked loop which enables adjustment of the delay through the digital delay line in fractions of a unit interval across variations due to differences in manufacturing process, operating voltage, and operating temperature. The disclosed techniques calibrate the digital delay lines by measuring both the high phase and the low phase of the clock signal. As a result, the disclosed techniques compensate for duty cycle distortion by combining the calibration results from both phases of the clock signal. The disclosed techniques thereby result in lower calibration error relative to approaches that measure only one phase of the clock signal.