Delay Line Output Stage With Duty Cycle Correction
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Solution Overview
Problem
Digitally-controlled delay line (DCDL) circuits with multiple stages face unsatisfactory output duty cycle due to unbalanced rise/fall times across stages, necessitating a mechanism to correct the duty cycle.
Innovation Solution
Incorporating a correction circuit with a second switch capacitor array that compensates for the intrinsic mobility characteristics of PMOS and NMOS in the delay line circuit, allowing for balanced rise/fall times and correcting the duty cycle by coupling the correction circuit with the output terminal of the first inverter cell and grounding the second terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple stages of DCDL are used to achieve multi-phase outputs, then the delay range and flexibility are improved, but the output duty cycle becomes unbalanced due to cumulative rise/fall time differences
Solution Approach 1:
A correction circuit is introduced as an intermediary component between the DCDL output and the final output. This correction circuit includes a second switch capacitor array that compensates for the duty cycle distortion by adjusting the output signal based on the accumulated rise/fall time differences from multiple DCDL stages
Solution Approach 2:
The correction circuit operates by detecting the duty cycle distortion caused by multiple DCDL stages and applying compensatory adjustments. The circuit uses feedback from the output signal to dynamically adjust the switch capacitor array, thereby correcting the duty cycle while maintaining the multi-phase output functionality
2Manufacturing precision
If correction circuit is added to correct duty cycle, then the output duty cycle accuracy is improved, but the device complexity increases
Solution Approach 1:
The correction circuit is designed to perform multiple functions: it corrects duty cycle distortion, maintains output signal integrity, and works across different DCDL configurations. The second switch capacitor array can be integrated with existing circuit elements, allowing the same structure to serve both correction and signal processing functions
Solution Approach 2:
The correction circuit is merged with the existing DCDL output stage by coupling the second switch capacitor array with the output terminal of the first inverter cell. This integration approach combines the correction functionality with the existing circuit architecture, reducing overall complexity compared to a separate correction system
Data Source
AI summary
The disclosure provides a delay line circuit including an output stage. The output stage includes a first inverter cell, a second inverter cell, a correction circuit, and a first switch capacitor array. The input terminal of the first inverter cell receives a reference clock signal. The input terminal of the second inverter cell is coupled with the output terminal of the first inverter cell. The first terminal of the correction circuit is coupled with the output terminal of the first inverter cell, and the second terminal of the correction circuit is coupled with a ground, wherein the correction circuit corrects a duty cycle of the delay line circuit. The first terminal of the first switch capacitor array is coupled with the output terminal of the second inverter cell, and the second terminal of the first switch capacitor array is coupled with the ground.