Delay Line Register Feedback for False Lock Detection
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Solution Overview
Problem
Delay locked loops often enter a false lock state where the delay is locked for two or more clock cycles, leading to incorrect operation, and there is a need for efficient techniques to sense and correct this state.
Innovation Solution
An electronic apparatus with a delay line comprising multiple delay elements and a register line, where phase signals are tapped off and used to detect false lock states through a phase frequency detector and evaluation register, producing error signals to adjust the delay and sense incorrect lock states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay locked loop uses a phase frequency detector to lock the delay of an input clock signal, then the delayed input clock signal is delayed by precisely one clock cycle, but the delay locked loop may enter a false lock state where it is locked for two or more clock cycles
Solution Approach 1:
The patent applies preliminary action by using a register line to capture and store the state of delay elements at specific clock edges before the locking decision is made. This allows the system to record the actual delay state in advance and compare it with the expected state, enabling detection of false lock conditions before they cause incorrect operation. The register elements store phase signals from delay elements, creating a historical record that can be evaluated to determine if the loop is truly locked or in a false lock state.
Solution Approach 2:
The patent implements feedback by continuously monitoring the output of register elements and using this information to control the delay locked loop operation. The phase frequency detector receives feedback about the lock state from the register outputs, and this feedback loop allows the system to detect when the actual delay diverges from the intended one-clock-cycle delay. The feedback mechanism enables real-time correction or detection of false lock conditions by comparing expected versus actual delay states.
2Reliability
If the delay locked loop locks for two or more clock cycles, then the delay is excessive, but detecting and correcting this false lock state requires additional sensing mechanisms
Solution Approach 1:
The patent applies universality by making the register line serve multiple functions: it stores phase signals from delay elements, provides feedback to the phase frequency detector, enables false lock detection, and maintains synchronization information. Rather than adding a separate dedicated sensing mechanism, the register elements perform multiple roles within the existing delay locked loop architecture. This multi-functional approach detects false lock states without proportionally increasing device complexity.
Solution Approach 2:
The patent implements self-service by using the existing components of the delay locked loop (delay elements, phase frequency detector, clock signals) to automatically detect and indicate false lock states. The register elements utilize the same clock signals and phase signals already present in the system, and the phase frequency detector uses its existing comparison functionality to evaluate lock state accuracy. The system detects false locks using its own internal resources without requiring external or additional specialized sensing equipment.
Data Source
AI summary
An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.