Programmable Delay Line Latch Timing for Glitch Suppression
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Solution Overview
Problem
Programmable delay lines in circuits often experience glitches when the delay time is adjusted, leading to errors in operation, particularly during critical sampling edges of clock transitions.
Innovation Solution
The implementation of programmable delay lines with latches triggered by input signal edges, coupled with capacitor and transistor subassemblies, which introduce a delay to prevent simultaneous updating and suppress glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay time is adjusted in a programmable delay line, then the adaptability of the delay line is improved, but glitches occur during adjustment causing operational errors
Solution Approach 1:
The patent applies preliminary action by triggering the latch with the edge of the input signal before the capacitor and transistor subassemblies can update during critical sampling edges. This advance triggering ensures the latch is ready to capture the correct signal state before any potential glitches from delay adjustments occur, thereby maintaining operational accuracy while allowing programmable delay changes.
2Speed
If latches are directly coupled to capacitor and transistor subassemblies without delay, then the response speed is improved, but simultaneous updating occurs causing glitches
Solution Approach 1:
The patent introduces an intermediary delay mechanism between the capacitor and transistor subassemblies and the latch. This delay, implemented through the specific coupling arrangement, prevents simultaneous updating by ensuring the latch triggers based on the input signal edge before the capacitor and transistor subassemblies complete their update cycle, thereby eliminating glitches while maintaining fast response.
3Device complexity
If the latch updates simultaneously with the capacitor and transistor subassemblies, then the device complexity is reduced, but errors occur during critical sampling edges
Solution Approach 1:
The patent applies preliminary action by configuring the latch to trigger on the edge of the input signal before the capacitor and transistor subassemblies update during critical sampling edges. This timing arrangement ensures the latch captures the correct signal state in advance, preventing errors while maintaining a relatively simple circuit structure without requiring complex control logic.
Data Source
AI summary
There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.