Programmable Delay Line Switching Without Glitches
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Solution Overview
Problem
Delay lines generate glitches due to switching delay paths in response to changes in control signals, causing timing violations in connected circuits due to device mismatch, routing mismatch, and process-voltage-temperature variations.
Innovation Solution
Implement a control circuit with first and second control signal generators that provide timing margins to prevent glitches by controlling the enablement of delay paths, using delay circuits to manage skew between control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay paths are switched in response to control signal changes, then the delay line can be programmed to different delay values, but glitches are generated due to device mismatch, routing mismatch, and PVT variations
Solution Approach 1:
The control circuit generates control signals in advance to ensure that delay paths are enabled before the actual switching occurs. The first control signal enables the first delay path before the second delay path is disabled, and the second control signal disables the second delay path after the first delay path is enabled, preventing glitches during the switching transition
Solution Approach 2:
The control circuit acts as an intermediary between the delay control signal and the delay paths. It generates intermediate control signals (first control signal and second control signal) that coordinate the enabling and disabling of delay paths, ensuring smooth transitions without glitches
2Speed
If control signals are switched simultaneously, then the switching speed is maximized, but timing violations occur due to skew between control signals
Solution Approach 1:
The control circuit prepares control signals in advance with appropriate timing margins. The first control signal is generated to enable the first delay path before the second delay path is disabled, and the second control signal is generated to disable the second delay path after the first delay path is enabled, ensuring timing accuracy while maintaining switching speed
Solution Approach 2:
The control circuit dynamically adjusts the timing of control signals based on the delay control signal transitions. It provides different timing margins for enabling and disabling delay paths, adapting to the dynamic switching requirements while maintaining timing accuracy
Data Source
AI summary
A control circuit outputs a first control signal and a second control signal to a first control input and a second control input, respectively, of a programmable delay circuit. In certain aspects, the control circuit receives a rising edge of a delay control signal. In response to the rising edge of the delay control signal, the control circuit outputs a rising edge of the first control signal and a falling edge of the second control signal after the rising edge of the first control signal. The control circuit also receives a falling edge of the delay control signal. In response to the falling edge of the delay control signal, the control circuit outputs a rising edge of the second control signal and outputs a falling edge of the first control signal after the rising edge of the second control signal.