Clocked Delay Line Frequency Divider With Low Duty Cycle Error
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Solution Overview
Problem
Existing frequency division circuits that provide odd number division ratios often suffer from significant duty cycle errors, leading to phase errors and degraded signal processing quality, particularly in applications like frequency synthesis and harmonic rejection mixing, and are typically costly due to the requirement of multiple multi-state circuits.
Innovation Solution
A signal processing circuit utilizing a clocked delay line with an enable circuit that introduces different delays for rising and falling edges, allowing for frequency division by an odd number with reduced duty cycle errors, achieved by adding a supplementary signal with a precise 180° phase relationship, and requiring fewer elements than previous solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a frequency division circuit uses two multi-state circuits to achieve frequency division by an odd number with small duty cycle error, then the signal processing quality is improved, but the device complexity and cost increase
Solution Approach 1:
The circuit is segmented into two functional parts: a standard delay line with latches for frequency division, and a separate enable circuit with D-type latches that selectively controls state changes. This segmentation allows the enable circuit to independently manage duty cycle correction without requiring a complete redesign of the frequency division logic, thereby reducing overall complexity while maintaining precision.
Solution Approach 2:
The enable circuit acts as an intermediary between the input signal and the latches in the delay line. It mediates the state changes of the latches by enabling or disabling them based on the previous state, thereby controlling the duty cycle of the output signal. This intermediary approach allows duty cycle correction without directly modifying the core frequency division mechanism.
2Manufacturing precision
If a frequency division circuit uses multiple multi-state circuits to achieve frequency division by an odd number, then the duty cycle error is reduced, but the quantity of circuit elements increases
Solution Approach 1:
The enable circuit serves multiple functions: it controls the duty cycle of the output signal, maintains the frequency division ratio by one-third, and ensures proper synchronization of latch state changes. By making the enable circuit multi-functional, the design avoids the need for separate dedicated circuits for each function, thereby reducing the total number of circuit elements while maintaining precision.
Solution Approach 2:
The latches in the delay line automatically adjust their behavior based on the enable signal from the enable circuit. The enable circuit uses the output of the delay line itself to control its own operation, creating a self-regulating system that corrects duty cycle errors without requiring external intervention or additional complex control logic.
3Manufacturing precision
If a frequency division circuit introduces different delays for rising and falling edges to achieve frequency division by an odd number, then the duty cycle accuracy is improved, but the device complexity increases
Solution Approach 1:
The delay mechanism is made dynamic through the enable circuit, which selectively enables or disables latches based on the previous state. Instead of using fixed different delays for rising and falling edges, the circuit dynamically adjusts which latches are enabled during each clock cycle, thereby achieving duty cycle accuracy through adaptive control rather than static delay differences.
Solution Approach 2:
The enable circuit changes the operational parameters of the latches by modifying their enable states. By changing the enable parameter based on the previous output state, the circuit effectively creates different delay behaviors for different signal transitions without requiring physically different delay paths, thereby maintaining simplicity while achieving precision.
Data Source
AI summary
A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.