Delay Line Packet Reordering for TDM Processing Engines
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Solution Overview
Problem
Parallel processing network systems face challenges in maintaining packet order due to varying processing times across different processing elements, leading to issues like audio signal loss or pixel disruption, and conventional solutions like fixed latency result in idle processing elements and wasted resources.
Innovation Solution
A network system incorporating an array of processing engines and a delay line for time division multiplexing sequencing, which includes an ingress circuit, a delay line, a demultiplexer, a tag memory, and a multiplexer to store and reorder packets based on unique tag values, ensuring packets exit in the original sequence without unnecessary delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed latency is enforced for each packet in a processing engine to ensure packet sequence, then packet ordering is maintained, but the processing engine must idle while waiting for packets to leave, wasting computing resources and reducing overall performance
Solution Approach 1:
The system segments the packet processing function into two independent parts: (1) the processing engine that processes packets at variable speeds without idle time, and (2) the delay line that handles packet reordering. This segmentation allows each component to optimize for its specific function, resolving the contradiction between maintaining order and maximizing throughput.
Solution Approach 2:
A delay line acts as an intermediary buffer between the processing engine and the output. The delay line stores processed packets temporarily and releases them in the correct sequence, mediating between the engine's variable-speed processing and the requirement for ordered output, thereby eliminating the need for the engine to idle.
2Productivity
If packets are processed in parallel by multiple processing elements, then processing throughput is improved, but packets may exit in different sequences from the original input order, causing data loss or disruption
Solution Approach 1:
The system adds a time dimension to the parallel processing architecture by introducing a delay line with multiple storage positions. Packets are distributed across different time slots in the delay line based on their original input order, allowing parallel processing to occur while maintaining sequence integrity through temporal separation.
Solution Approach 2:
The system uses tag values as copies of packet identification information to track and reorder packets. Each packet is associated with a unique tag that is stored in the delay line, allowing the system to identify and reconstruct the original packet sequence without physically tracking each packet through the parallel processing elements.
3Productivity
If processing elements operate without fixed latency constraints, then computing resources are fully utilized and throughput is maximized, but packets cannot be guaranteed to exit in the original input sequence
Solution Approach 1:
The packet reordering function is extracted from the processing engine and placed in a separate delay line component. This extraction allows the processing engine to focus solely on maximizing throughput without the constraint of maintaining packet sequence, while the delay line independently handles the reordering function using tag values.
Solution Approach 2:
The system performs preliminary tagging of packets with unique identification values before they enter the parallel processing stage. This preliminary action enables subsequent reordering based on the original input sequence, allowing the processing engine to operate at maximum throughput while the tagged packets can be reconstructed in the correct order afterward.
Data Source
AI summary
A network system, having an array of processing engines (“PEs”) and a delay line, improves packet processing performance for time division multiplexing (“TDM”) sequencing of PEs. The system includes an ingress circuit, a delay line, a demultiplexer, a tag memory, and a multiplexer. After the ingress circuit receives a packet from an input port, the delay line stores the packet together with a unique tag value. The delay line, in one embodiment, provides a predefined time delay for the packet. Once the demultiplexer forwards the packet to an array of PEs for packet processing, a tag memory stores the tag value indexed by PE number. The PE number identifies a PE in the array, which was assigned to process the packet. The multiplexer is capable of multiplex packets from PE array and replacing the packet with the processed packet in the delay line in response to the tag value.