Delay-Line Clock Phase Measurement Without Complex Calibration
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Solution Overview
Problem
Existing phase measurement technologies face challenges in accurately measuring phase differences between clock signals with integer ratios and low common frequencies, particularly when implemented in digital circuitry, as they require complex calibration processes and are prone to instability and power consumption issues.
Innovation Solution
A phase measurement circuitry using a delay line with multiple delay units connected in series, where signal edges of a first clock signal propagate, and an edge detector samples these edges based on a second clock signal to determine phase angles per delay unit, allowing for accurate phase measurement and error detection without the need for extensive calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase measurement is implemented in digital circuitry using existing technologies, then measurement can be performed, but complex calibration processes are required and stability deteriorates
Solution Approach 1:
The delay line is designed to automatically self-calibrate by using its own internal delay units to measure and compensate for process, voltage, and temperature variations. The system performs self-service calibration without requiring external calibration equipment or complex external procedures, thereby reducing calibration complexity while maintaining measurement precision.
Solution Approach 2:
The system implements a feedback mechanism where the measured phase information is used to adjust and compensate for PVT variations in real-time. The delay line continuously monitors its own performance and applies corrections through feedback loops, eliminating the need for complex external calibration processes and improving measurement stability.
2Measurement precision
If delay line is used for phase measurement, then phase measurement capability is provided, but PVT variations cause measurement errors
Solution Approach 1:
The system dynamically adjusts delay line parameters to compensate for PVT variations. By changing the effective delay characteristics through controlled adjustments of delay unit operations, the system maintains accurate phase measurement despite environmental changes. This parameter adaptation allows the delay line to counteract the effects of temperature, voltage, and process variations.
Solution Approach 2:
A feedback mechanism continuously monitors phase measurement accuracy and adjusts delay line operation to compensate for PVT variations. The system uses feedback loops to detect measurement deviations caused by environmental changes and applies real-time corrections, thereby maintaining measurement reliability under varying conditions.
3Adaptability or versatility
If high ratio m/n is used between clock frequencies, then frequency flexibility is improved, but common frequency becomes very low reducing measurement update rate
Solution Approach 1:
The system segments the phase measurement process into multiple independent delay units that can operate in parallel or series configurations. This segmentation allows the measurement function to be independent of the clock frequency ratio, enabling high m/n ratios while maintaining adequate measurement update rates through the modular architecture of the delay line.
Solution Approach 2:
The invention transitions from time-domain measurements constrained by clock frequencies to a spatial-domain approach using the delay line's physical structure. By measuring phase differences through spatial propagation delays rather than temporal sampling, the system achieves frequency ratio independence, allowing high m/n ratios without sacrificing measurement update rate.
4Use of energy by stationary object
If FIFO buffer size is reduced to optimise power and size, then power consumption and hardware size are improved, but phase error control becomes more critical
Solution Approach 1:
The delay line performs self-calibration and automatic compensation for phase errors, reducing the burden on external phase error control mechanisms. By serving its own calibration needs internally, the system enables smaller FIFO buffers while maintaining sufficient phase error control through the delay line's autonomous operation.
Solution Approach 2:
The system implements feedback control where phase measurement information from the delay line is used to adjust system operation and minimize phase errors. This feedback mechanism enables reduced FIFO buffer sizes by actively controlling phase errors based on real-time measurements, thereby reducing the need for large buffers while maintaining system reliability.
Data Source
AI summary
The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F1 and a second clock signal having an intended clock frequency F2, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.