Variable Delay Line Feedback for PVT-Stable Phase Delay

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Solution Overview

Problem

Existing delay circuits in integrated circuits struggle to maintain a consistent phase delay due to process, voltage, and temperature (PVT) variations, making it difficult to achieve a desired phase delay in signals.

Innovation Solution

A delay circuit comprising a variable delay line, first and second phase difference detectors, and a control circuit that adjusts the delay value based on detected phase differences between input and clock signals to maintain a target phase delay, using time-to-digital converters to generate codes for adjusting the delay value.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a general delay circuit is used to delay an input signal, then the delay circuit can provide basic delay functionality, but the delay amount changes depending on PVT variation making it difficult to achieve desired phase delay

Engineering Contradiction:
Improvephase delay accuracyVSAvoiddelay consistency under PVT variation
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where phase difference detectors continuously monitor the phase relationship between the input signal and clock signals, and a control circuit adjusts the delay amount based on these detections. This closed-loop feedback system compensates for PVT variations by dynamically adjusting the delay to maintain the desired phase relationship, thereby resolving the contradiction between delay accuracy and reliability under varying conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent employs variable delay lines that can dynamically change their delay parameter based on control signals. By adjusting the delay parameter in response to detected phase differences, the system adapts to PVT variations and maintains consistent phase delay performance, thus improving both measurement precision and reliability simultaneously.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a variable delay line with adjustable delay value is used, then the delay can be adjusted to compensate for PVT variation, but the device complexity increases due to additional phase difference detectors and control circuits

Engineering Contradiction:
Improvedelay consistency under PVT variationVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs the delay circuit components to serve multiple functions. The variable delay line not only provides delay functionality but also responds to control signals for adaptation. The phase difference detectors serve both measurement and control purposes. This multi-functionality reduces the need for separate dedicated components, thereby mitigating the increase in device complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The delay circuit implements self-adjustment capability where the system automatically detects phase differences and adjusts its own delay parameter without external intervention. This self-service mechanism eliminates the need for complex external calibration equipment or manual adjustment mechanisms, reducing overall system complexity while ensuring consistent performance under PVT variation.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10644707B2Delay circuit
Publication Date: 2020.05.05 SK HYNIX INC
  • US10644707B2 patent drawing
  • US10644707B2 patent drawing
  • US10644707B2 patent drawing

AI summary

A delay circuit includes: a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.