Delay Line Phase Inverter Layout for Duty Cycle Symmetry
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Solution Overview
Problem
Conventional delay lines in delay lock loops suffer from non-linearity and duty cycle symmetry issues due to the use of two inverting gates in each delay stage, leading to excessive power consumption and reduced phase mixer linearity.
Innovation Solution
A delay line with single NAND gates in each stage, combined with a phase inverter to ensure equal propagation delay for both rising and falling edges, reducing the coarse step size and improving phase mixer linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If two inverting gates are used in each delay stage, then duty cycle symmetry is improved, but power consumption increases and non-linearity is introduced
Solution Approach 1:
The patent removes one inverting gate from each delay stage, extracting the source of excessive power consumption while maintaining duty cycle symmetry through the phase inverter mechanism. This reduces the number of active devices in the delay path, directly lowering dynamic power consumption.
Solution Approach 2:
The phase inverter acts as an intermediary component that compensates for the asymmetry introduced by using only a single NAND gate. It restores duty cycle symmetry by inverting the phase of the output signal, thereby maintaining stable composition without requiring two inverting gates in the delay stage.
2Stability of the object's composition
If two inverting gates are used in each delay stage, then duty cycle symmetry is improved, but non-linearity increases
Solution Approach 1:
By removing one inverting gate from the delay stage, the patent reduces the total number of non-linear elements in the signal path. Fewer gates mean fewer sources of propagation delay variation, thereby improving phase mixer linearity while the phase inverter maintains duty cycle symmetry.
Solution Approach 2:
The phase inverter serves as a mediator that corrects the duty cycle asymmetry caused by the reduced gate count. This allows the delay line to use simpler, more linear gate structures without sacrificing duty cycle stability, thus improving overall system linearity.
3Use of energy by moving object
If single NAND gates are used in each delay stage, then power consumption is reduced and linearity is improved, but duty cycle symmetry deteriorates
Solution Approach 1:
The phase inverter acts as a corrective intermediary that takes the asymmetric output from the single-NAND-gate delay stage and restores duty cycle symmetry. This allows the system to benefit from the lower power consumption and improved linearity of the simplified delay stage while maintaining stable duty cycle composition.
Solution Approach 2:
The patent segments the delay function into two parts: the single NAND gate provides the primary delay with reduced power consumption, while the phase inverter handles the duty cycle correction. This segmentation allows each component to be optimized for its specific function.
4Manufacturing precision
If single NAND gates are used in each delay stage, then phase mixer linearity is improved, but coarse step size increases
Solution Approach 1:
The phase inverter enables the use of single NAND gates in delay stages by compensating for the resulting duty cycle asymmetry. This allows the system to achieve better phase mixer linearity while the coarse step size is managed through the overall delay line design and phase detector feedback mechanism.
Data Source
AI summary
Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.