High-Speed Delay Line Power-Up Sequencing for Low Supply Noise
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Solution Overview
Problem
High-speed clock/timing circuits, such as DLL and DCC, face challenges with high power consumption and voltage fluctuations due to the simultaneous activation of all delay cells, leading to increased current spikes and instability in the internal clock signal, which affects the locking time and overall performance.
Innovation Solution
Implementing a digital locking-search state machine to gradually turn on delay cells one by one or in small subgroups, reducing power consumption and minimizing current spikes, and using control circuitry to manage phase locking and power-up of delay cells incrementally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all delay cells are turned on simultaneously when DLL and DCC are activated, then locking time is reduced and internal clock stability is improved, but large surge current and voltage jumps occur causing power supply noise
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors connected to delay cells before activating them. When a delay cell is selected, its associated capacitor is already charged, preventing sudden current surges. This is implemented through control circuitry that charges capacitors in advance based on shift register states, ensuring that when delay cells are turned on, no large inrush current occurs, thus eliminating power supply noise while maintaining clock stability.
2Adaptability or versatility
If the quantity of delay cells is increased to cover wider locking frequency ranges, then frequency range coverage is improved, but total current consumption increases
Solution Approach 1:
The patent applies local quality by making different delay cells have different operational states - some are active while others are powered down. The control circuitry selectively activates only the necessary delay cells based on the required frequency range, rather than keeping all delay cells continuously active. This is achieved through shift register control that enables specific delay cells only when needed, reducing overall power consumption while maintaining wide frequency range coverage capability.
3Speed
If differential type delay cells are used for high speed operation, then voltage swing is reduced improving speed, but DC current consumption increases
Solution Approach 1:
The patent applies dynamics by making the delay cell configuration changeable - switching between differential and single-ended types based on operational requirements. The control circuitry can dynamically select which type of delay cell to activate, allowing the system to use differential cells for high-speed operations when needed and single-ended cells for low-power modes when speed is less critical. This dynamic reconfiguration enables optimization of both speed and power consumption depending on the operational context.
Data Source
AI summary
The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.