Delay-Line Pulse Generator for Precise Width Without Fast Clocks
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Solution Overview
Problem
Traditional pulse signal generation methods in digital circuits are inefficient in terms of power and circuit area, as they rely on high-speed clocks or large-area consuming solutions, leading to inaccurate pulse widths and potential errors in downstream operations.
Innovation Solution
A width-controllable pulse generator using a delay line with multiple stages, where the per-stage delay is measured and used to generate pulses of precise width, independent of the input clock frequency, allowing for accurate small pulse width generation without the need for power-consuming fast clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high-speed clock methods are used for pulse generation, then pulse width accuracy is improved, but power consumption increases
Solution Approach 1:
The patent changes the fundamental parameter used for pulse generation from clock frequency to delay time. By measuring the actual per-stage delay of the delay line and using this measured value to calculate the number of stages needed for the desired pulse width, the system achieves accurate pulse width control without relying on high-speed clocks, thereby reducing power consumption while maintaining precision.
Solution Approach 2:
The patent replaces the mechanical/clock-based pulse generation mechanism with a delay-line-based timing mechanism. Instead of using high-frequency clock cycles to define pulse width, the system uses controlled signal propagation through multiple delay stages, where the pulse width is determined by the number of stages traversed rather than by clock frequency, eliminating the need for power-consuming fast clocks.
2Measurement precision
If traditional high-speed clock methods are used for pulse generation, then pulse width accuracy is improved, but circuit area increases
Solution Approach 1:
The patent segments the pulse generation function into multiple independent delay stages, where each stage contributes a fixed delay amount. By dividing the total required delay into discrete stages and selectively enabling them based on the desired pulse width, the system achieves accurate timing control using simple, repetitive units rather than complex high-speed clock circuitry, reducing overall circuit area.
3Ease of operation
If fixed clock frequency is used, then circuit operation is simplified, but pulse width adaptability is reduced
Solution Approach 1:
The patent introduces dynamic configurability to the delay line by allowing individual stages to be selectively enabled or disabled based on the desired pulse width. This dynamic control mechanism enables the same delay line infrastructure to adapt to different pulse width requirements without changing the clock frequency or fundamental circuit operation, achieving both simplicity and versatility.
Data Source
AI summary
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.