Delay-Line Pulse Generator for Precise Width Without Fast Clocks
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Solution Overview
Problem
Traditional pulse signal generation methods in digital circuits are inefficient in terms of power and circuit area, as they rely on high-speed clocks or large-area consuming solutions, leading to inaccurate pulse widths and potential errors in downstream operations.
Innovation Solution
A width-controllable pulse generator using a delay line with multiple stages, where the per-stage delay is measured and utilized to generate pulses of precise width, independent of the input clock frequency, allowing for accurate small pulse width generation without the need for power-consuming fast clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-speed clocks are used for pulse signal generation, then pulse width accuracy is improved, but power consumption increases
Solution Approach 1:
The pulse generation function is segmented into multiple delay stages, where each stage contributes a portion of the total delay. By selecting and combining specific stages, the desired pulse width is achieved without requiring a high-speed clock, thus reducing power consumption while maintaining accuracy.
Solution Approach 2:
Delay values for each stage are pre-calculated and stored in lookup tables based on the desired pulse width. This preliminary computation eliminates the need for real-time high-speed clock operations, reducing power consumption while ensuring accurate pulse width generation.
2Measurement precision
If high-speed clocks are used for pulse signal generation, then pulse width accuracy is improved, but circuit area increases
Solution Approach 1:
The circuit is divided into multiple delay stages with selectable outputs. Instead of using a single high-speed clock circuit that occupies large area, the segmented approach uses simpler delay elements that collectively achieve the same functional accuracy with reduced total area.
Solution Approach 2:
Lookup tables storing pre-calculated delay values are used instead of complex real-time computation circuits. This copying of pre-computed data into accessible memory structures reduces the need for large-area high-speed clock generation and control logic.
3Ease of manufacture
If clock frequency-dependent pulse generation is used, then implementation simplicity is improved, but pulse width accuracy deteriorates
Solution Approach 1:
Delay characteristics are pre-calculated and stored in lookup tables during design time. This preliminary action separates the complex computation from runtime operation, maintaining implementation simplicity while achieving high pulse width accuracy through pre-computed optimal delay values.
Solution Approach 2:
The system incorporates feedback mechanisms where the actual pulse width is measured and compared against the desired width. Based on this feedback, the appropriate delay stages are selected to compensate for variations, ensuring accurate pulse width generation while maintaining simple implementation through automated control.
Data Source
AI summary
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.