Delay Line Calibration Using Derived Reference Clock Signals
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Solution Overview
Problem
Current digital delay line calibration systems fail to account for various sources of inaccuracy, leading to inaccuracies in delay line signal timing and accuracy due to duty cycle distortion, mismatches between reference and delayed clocks, and phase detector errors caused by PVT variations and on-chip variations.
Innovation Solution
The system synchronizes the delay line signal to a delayed version of a reference clock and inverts the reference clock to compensate for mismatches and phase detector biases, using derived reference signals to adjust the delay line calibration, thereby addressing skew components and duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional delay line calibration systems are used, then the system structure is simple, but calibration accuracy deteriorates due to unaccounted sources of inaccuracy such as duty cycle distortion, clock mismatches, and phase detector errors
Solution Approach 1:
The patent introduces derived reference signals as an intermediary between the original reference clock and the delay line calibration process. These derived signals (inverted reference clock, delayed reference clock) act as mediators that compensate for various error sources including duty cycle distortion and clock path mismatches, thereby improving calibration accuracy without requiring fundamental changes to the overall system architecture
Solution Approach 2:
The patent changes the parameters of the reference clock signal by generating derived reference signals with different characteristics (inverted phase, delayed timing). This allows the calibration system to account for PVT variations and on-chip variations by comparing multiple signal versions, improving measurement precision while maintaining reasonable system complexity
2Adaptability or versatility
If the delay line operates across different PVT corners, then the adaptability improves, but the calibration accuracy deteriorates due to PVT variations and on-chip variations introducing biases
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector compares the delay line output with multiple derived reference signals and adjusts the delay line calibration accordingly. This feedback loop continuously compensates for PVT variations and on-chip variations, maintaining calibration accuracy across different operating conditions and PVT corners
Solution Approach 2:
The patent performs preliminary actions by pre-generating multiple derived reference signals (inverted, delayed versions) before the actual calibration process. These pre-prepared signals anticipate and compensate for expected PVT variations and on-chip variations, allowing the system to maintain accuracy across different PVT corners without requiring real-time complex adjustments
3Measurement precision
If duty cycle distortion is present in clock signals, then the clock signal generation remains simple, but the timing accuracy deteriorates affecting phase detection and calibration locking
Solution Approach 1:
The patent uses derived reference signals as intermediaries to transfer and compare timing information without being directly affected by duty cycle distortion in the original clock signals. By comparing phase relationships across multiple derived signal versions, the system achieves accurate timing measurement while filtering out the harmful effects of duty cycle variations
Solution Approach 2:
The patent changes the temporal parameters of the reference clock by creating inverted and delayed versions. This transformation allows the system to measure timing accuracy independent of the original clock's duty cycle characteristics, as the phase relationships remain consistent even when duty cycle varies
Data Source
AI summary
Techniques for improving the accuracy of delay line calibration schemes. For example, an amount of offset may be determined between one or more first portions of a first clock signal and one or more second portions of a second clock signal that is delayed relative to the first clock signal. The first portion(s) may correspond to the second portion(s) based at least on the second clock signal being delayed relative to the first clock signal. In some examples, a value may be determined based at least on the amount of offset. The value may correspond to an amount to adjust the first clock signal to reduce the amount of offset. In some examples, a delay line may then be calibrated, based at least on the second value, to adjust the first clock signal.