Delay-Line Inter-Die Communication for Low-Power High-Speed SerDes
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Solution Overview
Problem
There is a need for reliable, low-power serializer and deserializer circuits to support high-speed serial communications within and between integrated circuits (ICs), as existing technologies face challenges in achieving high data throughput with reduced power consumption.
Innovation Solution
The proposed solution involves a low-power, high-speed serializer circuit and deserializer circuit, each utilizing a delay line, buffers, and a clock generation circuit. The serializer generates N delay line signals to enable buffers to transmit data bits over a serial communication link, while the deserializer uses delay lines and latches to capture data bits and regenerate a transmit clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional serializer and deserializer circuits are used to achieve high data throughput, then communication speed is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic clock signals with variable frequencies to control the operation of buffers and latches in the serializer and deserializer. By using periodic action with adjustable frequency, the circuit achieves high data throughput when needed while allowing frequency reduction to lower power consumption during normal operation, directly resolving the contradiction between productivity and energy use.
Solution Approach 2:
The patent implements dynamic frequency adjustment of the clock signal based on communication needs. The clock generation circuit can vary the frequency dynamically, allowing the system to operate at high speeds when data throughput is required while switching to lower frequencies to minimize power consumption during idle or low-traffic periods, thus resolving the contradiction between speed and power usage.
2Productivity
If high-frequency clock signals are used to increase data transmission speed, then communication rate is improved, but jitter accumulation increases
Solution Approach 1:
The patent uses periodic clock signals with carefully controlled frequencies to synchronize data transmission. The periodic nature ensures that data bits are sampled at consistent intervals, reducing timing jitter. By optimizing the frequency and duty cycle of these periodic signals, the system achieves high communication rates while maintaining signal integrity and minimizing jitter accumulation.
Solution Approach 2:
The patent incorporates feedback mechanisms in the clock generation and recovery circuits to detect and correct timing deviations. The feedback loops monitor the actual timing of transmitted and received signals, making real-time adjustments to compensate for jitter, thus enabling high communication rates without excessive jitter accumulation.
Data Source
AI summary
A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.