Delay-Line Inter-Die SerDes for Low-Power High-Speed Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for low-power, high-speed serializer and deserializer circuits to support efficient serial communication between integrated circuits, as existing solutions consume high power and are not optimized for reduced footprints in mobile electronic devices.
Innovation Solution
The proposed solution involves serializer circuits with a delay line, buffers, and a clock generation circuit that generate N delay line signals to enable data transmission, and deserializer circuits with delay lines, latches, and a clock generation circuit to regenerate the transmit clock signal, both designed to reduce power consumption and eliminate the need for flipflops, thereby minimizing jitter accumulation and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional serializer/deserializer circuits are used, then data transmission function is achieved, but power consumption is high
Solution Approach 1:
The patent extracts and eliminates the clock generation circuit from the serializer/deserializer interface. By removing this power-consuming component and using delay line signals directly to control buffers and latches, the circuit achieves low-power operation while maintaining high-speed data transmission capability through the inter-die communication link.
Solution Approach 2:
The delay line signals serve dual purposes: they provide timing control for data serialization/deserialization and simultaneously generate the clock signal locally at the receiver. This self-service approach eliminates the need for separate clock distribution and reduces power consumption by avoiding redundant clock circuitry.
2Productivity
If high-speed serial communication is implemented, then data throughput is increased, but power consumption increases
Solution Approach 1:
The patent uses periodic delay line signals generated at specific intervals (e.g., 1/8th of the clock period) to control buffer enabling and data latching. This periodic action synchronized with the data stream allows high-speed operation while minimizing the duration that power-consuming elements remain active.
Solution Approach 2:
The patent changes the operational parameters by using delay line signals with specific timing characteristics (delayed by precise intervals) to control the serialization process. This parameter optimization enables high-speed data transmission while reducing the active time of power-consuming circuit elements.
3Adaptability or versatility
If serializer/deserializer circuits are added to IC devices, then communication capability is enhanced, but device complexity increases
Solution Approach 1:
The delay line signals serve multiple functions simultaneously: they control buffer enabling for data serialization, provide timing references for deserialization, and generate clock signals for the receiving device. This multi-functionality reduces the need for separate dedicated circuits and simplifies the overall device architecture.
Solution Approach 2:
The patent merges the clock generation function with the data timing control function by using the same delay line signals for both purposes. This consolidation eliminates redundant circuitry and reduces device complexity while maintaining full communication capability.
Data Source
AI summary
A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.