Digitally Controlled Delay Line With Single-Polarity Tunable Stages
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Solution Overview
Problem
Existing digitally controlled delay lines (DCDLs) face challenges in achieving linear delay time control due to variations in transistor switching speeds, particularly when handling signals with both rising and falling transitions, leading to increased circuit size and complexity.
Innovation Solution
The implementation of single-sided tunable delay cells within DCDL circuits, where each signal path includes a tunable delay cell receiving the same signal transition polarity, reduces circuit complexity and process variation effects by configuring delay times based on same-type transistor switching speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional delay stages with both rising and falling transition handling are used, then comprehensive signal processing is achieved, but circuit size and complexity increase
Solution Approach 1:
The patent extracts only the necessary functionality for handling a single transition polarity (either rising or falling) in each delay stage, removing the redundant circuitry required for handling both polarities. This is achieved by using transmission gates configured to respond to only one transition type, thereby reducing circuit complexity while maintaining adequate signal processing capability for the intended application
Solution Approach 2:
Instead of designing delay stages that handle both rising and falling transitions conventionally, the patent inverts the approach by designing stages that specialize in handling only one transition polarity. The return path is configured to complement this specialization, creating a balanced system that achieves comprehensive signal processing through asymmetric stage design
2Adaptability or versatility
If delay stages are configured to handle both rising and falling transitions, then full signal coverage is achieved, but delay time linearity deteriorates due to transistor switching variations
Solution Approach 1:
The patent applies local quality by configuring different delay stages with specialized characteristics - some stages are optimized for rising transitions while others are optimized for falling transitions. This local specialization ensures that each stage contributes consistently to the overall delay, improving delay time linearity by eliminating the variability introduced by stages attempting to handle both transition types with generic circuitry
Solution Approach 2:
Within each delay stage, the patent uses transmission gates and logic elements of the same transistor type (either all n-type or all p-type) to handle a specific transition polarity. This homogeneity in transistor characteristics within each stage eliminates the delay variations that occur when mixed transistor types with different switching speeds are used, thereby improving delay time linearity
3Adaptability or versatility
If conventional delay line configuration is used, then programmable delay functionality is provided, but differential nonlinearity increases
Solution Approach 1:
The patent segments the delay line into multiple delay stages, where each stage is responsible for a specific portion of the total delay and is optimized for a specific transition polarity. This segmentation allows for more precise control of the delay contribution from each stage, reducing the cumulative differential nonlinearity that occurs in conventional unified delay lines. The control logic selectively activates appropriate stages based on the desired delay and input signal characteristics
Data Source
AI summary
A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.