Digital Delay Line Driver With Dynamic Slew and Crowbar Current Control
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Solution Overview
Problem
Digital delay line drivers face issues with crowbar current and dynamic slew rate control, leading to power inefficiency and noise in microchips, especially in high-speed circuits, due to the sensitivity of transition times to temperature and manufacturing variations.
Innovation Solution
The digital delay line driver incorporates circuitry to control the di/dt of supply current and reduce crowbar current by simultaneously turning off output line transistors, while allowing dynamic and variable slew rate control through control bits and accompanying circuitry that can drive the delay line at multiple points, thereby reducing noise and improving power supply stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple inverter design is used for digital driver, then the circuit is simple and small, but the edge speed is very sensitive to variations in temperature, power supply voltage, and manufacturing parameters resulting in timing uncertainty and potentially very high di/dt and peak currents
Solution Approach 1:
The patent divides the single inverter stage into multiple cascaded inverter stages (typically 3-5 stages). Each stage contributes to the overall delay, allowing the total transition time to be controlled by the number and characteristics of individual stages. This segmentation reduces sensitivity to process variations because the delay is distributed across multiple stages rather than concentrated in a single critical stage.
Solution Approach 2:
The patent introduces dynamic control of the inverter stages through enable signals and control logic. Each inverter stage can be independently enabled or disabled, allowing dynamic adjustment of the delay profile. This dynamic control enables adaptation to different operating conditions and reduces timing uncertainty by selecting optimal stage combinations based on temperature, voltage, and process variations.
2Speed
If fast transitions are used in digital interface, then higher-speed circuits are achieved, but crosstalk and electromagnetic interference increase
Solution Approach 1:
The patent implements dynamic slew rate control that adjusts the transition speed of output signals based on operating conditions. By controlling the enable signals timing and the activation of different inverter stages, the circuit can optimize the balance between speed and signal integrity, reducing crosstalk and electromagnetic interference when necessary while maintaining high speed when conditions allow.
3Speed
If fast rise time in transient supply current is used, then higher-speed operation is achieved, but the resonant circuit is excited causing ringing on the supply voltages
Solution Approach 1:
The patent uses dynamic control of the inverter stage enable signals to shape the transient current profile. By carefully timing the activation and deactivation of different stages, the circuit can control the rate of change of supply current (di/dt), preventing excitation of the resonant circuit formed by bond wire inductance and on-chip capacitance, thereby reducing ringing while maintaining high-speed operation.
4Speed
If large peak amplitudes in transient currents are used, then faster switching is achieved, but power supply droop increases due to finite resistance of supply wires
Solution Approach 1:
The patent segments the switching action across multiple inverter stages that activate in sequence rather than simultaneously. This staged activation distributes the current demand over time, reducing peak amplitudes and preventing excessive power supply droop while still achieving fast overall switching. The segmented approach allows the supply network to respond more gracefully to the distributed current draw.
Solution Approach 2:
The patent implements dynamic control of current draw through timed enable signals that activate different inverter stages at optimized moments. This dynamic current management shapes the transient current profile to minimize peak amplitudes and reduce power supply droop, while maintaining fast switching performance through coordinated stage activation.
Data Source
AI summary
Improved digital delay line driver is described. A delay line driver circuit includes elements to drive the delay line in one or multiple locations to provide a dynamic, adjustable slew rate on the output signal. The delay line driver circuit may also include active elements coupled to the transistors of the delay line to deactivate the delay line transistors substantially simultaneously, rather than cascading in series. Shutting off the delay line transistors substantially simultaneously reduces or eliminates crowbar or shoot through current on an edge transition of the output signal.