Digital Delay Line Slope ADC for Fast Low-Power Conversion
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Solution Overview
Problem
Current low-resolution, high-speed analog-to-digital converters (ADCs) are not power efficient, especially for high-speed applications, and require substantial calibration that is cumbersome and dependent on environmental conditions.
Innovation Solution
An asynchronous clocked slope ADC architecture that generates the slope in the digital domain using a digital delay line, eliminating the need for an oversampled clock and allowing for high-speed operation with minimal calibration, featuring programmable capacitors for offset correction and a simple, mostly digital implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash or folding topologies are used for high-speed low-resolution ADCs, then speed of operation is improved, but power efficiency deteriorates
Solution Approach 1:
The patent replaces the traditional analog slope generation mechanism with a digital delay line that generates the slope in the digital domain. This substitution of digital logic for analog circuitry enables high-speed operation while maintaining power efficiency, as digital circuits can operate at higher speeds with lower power consumption compared to the analog comparison mechanisms used in flash or folding ADCs.
2Measurement precision
If substantial calibration techniques are used to correct comparator offsets, then measurement precision is improved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The patent implements self-calibration through the digital delay line architecture, where the system automatically compensates for comparator offsets and latency variations without requiring external calibration equipment or complex calibration procedures. The digital domain processing inherently corrects for these errors, making the system self-correcting and eliminating the need for substantial manual calibration techniques.
3Use of energy by moving object
If traditional slope ADC with oversampled clock is used, then power efficiency is improved, but speed of operation deteriorates
Solution Approach 1:
The patent replaces the traditional analog slope generation and comparison mechanism with a digital delay line that operates asynchronously. This digital implementation eliminates the need for oversampled clocks while maintaining the power efficiency benefits of slope ADC, enabling high-speed operation through digital logic's inherent speed advantages.
4Speed
If digital delay line is used to generate slope in digital domain, then speed of operation is improved, but device complexity improves (becomes simpler)
Solution Approach 1:
The patent substitutes complex analog circuitry with a relatively simple digital delay line implementation. The digital delay line consists of basic digital logic elements that can be easily implemented in standard CMOS technology, reducing overall device complexity while enabling high-speed operation through the inherent speed advantages of digital circuits over analog circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high-speed operation with improved power efficiency and reduced calibration needs, maintaining accuracy despite latency variations, and achieves a Figure of Merit (FoM) of 130fJ per conversion step without additional calibration.
Implementation Method 1
The sampled version of the input signal is then applied to an array of capacitors
Data Source
Figure 1
Figure 2A~2C
Figure 3~4
AI summary
The present invention is related to an analog to digital converter circuit (1). The converter circuit comprises at least one input node (2) for applying an analog input voltage signal (Vin), sampling means (3) for sampling said analog input voltage signal, a first array of capacitors (5) arranged for receiving the sampled analog input voltage signal (4), a digital delay line (6) connected to the first array of capacitors (5) and arranged for being enabled by a clock generator (7) and for generating a staircase or slope function by means of the first capacitor array, taking into account the sampled analog input voltage signal, a comparator (8) arranged for comparing a converted signal (9) with a reference voltage (Vref), said converted signal being a version of said sampled analog input voltage (4) converted according to said staircase or slope function, and for generating a stop signal (10) based on the comparison result thereby latching the digital delay line and thereby acquiring the digital code.