Delay Line Test Circuit for Precise Stage Delay Measurement
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Solution Overview
Problem
Existing delay lines in semiconductor devices face challenges in accurately measuring small delay amounts, making it difficult to detect failures such as short-circuits between adjacent bits, due to the small difference in delay setting signals, which complicates the testing and adjustment of timing in high-speed data transfer standards like DDR.
Innovation Solution
A delay circuit with a logic circuit and a test system that uses a test signal and test control signal to measure the delay amount by integrating the output from a logic circuit, allowing for precise detection of delay faults through voltage measurement, enabling accurate measurement of delay per stage in the delay line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of delay elements is increased to achieve large maximum delay amount, then the delay range is improved, but the circuit complexity increases
Solution Approach 1:
The delay line is divided into multiple delay elements connected in series, where each delay element provides a small, fixed delay amount. By selectively connecting different numbers of delay elements, the circuit achieves variable delay amounts across a large range without requiring each individual element to provide large delay, thus managing circuit complexity while expanding delay range.
Solution Approach 2:
Instead of increasing the delay amount of individual elements (one dimension), the patent uses multiple small delay elements connected in series (adding another dimension through quantity arrangement). This allows achieving large total delay by combining many small delays, resolving the contradiction between individual element size and total delay range.
2Measurement precision
If the delay amount per stage is reduced to achieve high accuracy, then the measurement precision is improved, but the number of stages must be increased
Solution Approach 1:
The total delay is segmented into multiple small, equal-sized delay elements. Each element provides a small, precise delay amount that can be accurately controlled and measured. By using many such small segments rather than fewer large ones, the circuit achieves high measurement precision for each stage while the total delay is obtained through cumulative effect of all stages.
3Measurement precision
If the delay setting signal difference between adjacent bits is small, then the delay accuracy is improved, but the fault detection capability deteriorates
Solution Approach 1:
Before actual operation, a test mode is activated where test signals are applied to the delay line. During this preliminary testing phase, the small differences in delay settings between adjacent bits are deliberately measured and verified. This preliminary action ensures that despite the small signal differences, any faults such as short circuits between adjacent bits can be detected before the device enters normal operation mode.
Data Source
AI summary
A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.