Delay Line Tap Calibration Using Reference Tap Alignment
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Solution Overview
Problem
The non-linearity of delay lines makes it challenging to determine which tap to use for reliably sampling a data signal, as each delay element introduces a different amount of delay, and existing solutions that reduce non-linearity are resource-intensive.
Innovation Solution
A calibration method and circuit that utilize a reference circuit with finer taps to align output signals from the delay line, storing tap data to determine suitable taps for aligning edges or phases, allowing for the selection of appropriate taps for sampling data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay lines are designed to reduce non-linearity, then delay accuracy is improved, but circuit resource cost increases
Solution Approach 1:
The patent applies preliminary action by performing delay calibration before actual operation. A calibration circuit determines the actual delay values of each tap in advance and stores them in a calibration data structure. During normal operation, the pre-calibrated data is used to compensate for non-linearity, avoiding the need for complex hardware designs while maintaining high delay accuracy.
2Adaptability or versatility
If each delay element introduces different delay amounts, then flexibility in timing adjustment is improved, but difficulty in determining correct tap increases
Solution Approach 1:
The patent implements feedback through an iterative calibration process. The calibration circuit sequentially tests each delay tap, compares the actual delay against target values, and adjusts the calibration data accordingly. This feedback mechanism automatically determines the correct tap settings despite non-linear delay characteristics, eliminating the difficulty of manual tap selection while preserving timing flexibility.
Data Source
AI summary
In an approach for calibrating a delay line having a plurality of taps, a first clock signal is input to the delay line. A second clock signal is input to a reference circuit having a plurality of taps. In response to determining that output signals of selected taps of the delay line and reference circuit do not align, a next tap of the reference circuit is selected, to determine whether or not the output signals align. In response to determining that the output signals align, reference tap data indicative of the current reference tap is stored in association with a delay tap number of the current delay tap. A next tap of the delay line is selected to determine whether or not the output signals align.