Delay-Locked Loop Tap Switching for Faster Clock Locking
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in synchronizing internal clock signals with externally-generated clock signals due to time delays, requiring additional circuits that increase chip size and thermal dissipation, and existing methods either need duty cycle correction circuits or additional logic for successful synchronization.
Innovation Solution
A delay locked loop (DLL) circuit that selects a feedback quantity from a first intermediate location for initial synchronization and then switches to a second location for maintaining synchronization, reducing the need for additional circuits and logic, thereby achieving faster synchronization without increasing chip size or thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DLL circuits are used to synchronize internal and external clock signals, then synchronization is achieved, but additional circuits and logic are required which increase chip size and thermal dissipation
Solution Approach 1:
The patent extracts and eliminates the duty cycle correction circuit from the traditional DLL architecture. By using a simplified delay line with tap points that directly provide feedback signals to the phase detector, the circuit achieves clock synchronization without requiring the separate duty cycle correction functionality, thereby reducing chip area.
Solution Approach 2:
The delay line elements in the patent serve multiple functions simultaneously: they provide delay for phase adjustment and also generate feedback signals for both phase detection and duty cycle correction. This multi-functionality eliminates the need for separate correction circuits, reducing overall chip size while maintaining synchronization reliability.
2Reliability
If traditional DLL circuits with duty cycle correction are used, then synchronization is achieved, but additional logic circuits are required which increase device complexity
Solution Approach 1:
The patent merges the phase detection and duty cycle correction functions into a single integrated approach. The feedback signals taken from intermediate tap points of the delay line serve both purposes simultaneously, eliminating the need for separate correction logic and reducing overall device complexity.
Solution Approach 2:
The delay line elements self-generate the necessary feedback signals at their intermediate tap points. These signals automatically provide both phase information and duty cycle correction information to the phase detector, eliminating the need for external correction circuits and simplifying the overall device logic.
3Reliability
If conventional synchronization methods are used, then clock signals are synchronized, but synchronization time is extended which reduces productivity
Solution Approach 1:
The patent takes preliminary action by providing multiple feedback signals from intermediate tap points before the full synchronization process completes. This allows the phase detector to anticipate phase differences and make earlier adjustments, accelerating the synchronization process while maintaining accurate phase alignment.
Solution Approach 2:
The patent implements enhanced feedback by tapping signals from multiple intermediate points in the delay line and feeding them to the phase detector. This provides richer feedback information that enables faster convergence to the locked state, improving synchronization speed without sacrificing phase alignment accuracy.
Data Source
AI summary
Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.