Delay-Line Time Capture Circuit for High-Resolution Timing

The patent segments the timing measurement function into two parts: a low-frequency system clock for general operation and a high-frequency delay line clock for precise timing intervals. This segmentation allows the system to achieve high timing resolution only when needed for measurements, rather than continuously running at high frequency, thus reducing overall power consumption while maintaining measurement precision.

The patent implements dynamic clock switching where the delay line clock frequency can be independently configured and activated only during timing measurement operations. The system dynamically transitions between low-power mode (system clock only) and high-precision mode (delay line clock activated), optimizing the balance between timing resolution and power consumption based on operational requirements.

The patent separates the high-frequency timing function into an independent delay line clock domain, isolated from the main system clock domain. This segmentation confines high-frequency noise generation to a localized, controlled portion of the circuit, preventing noise propagation to other system components while maintaining the ability to achieve high timing resolution in measurements.

The delay line clock operates periodically only during timing measurement intervals rather than continuously. This periodic activation reduces the overall noise emission by limiting high-frequency operations to brief measurement windows, while still achieving the required timing resolution when measurements are performed.

The patent divides the timing resolution enhancement into a dedicated delay line module with its own clock, separate from the main system clock infrastructure. This segmentation allows the high-frequency delay line to be implemented as a compact, specialized circuit block rather than requiring the entire system to operate at high frequency, thus minimizing the additional die area required for high-resolution timing capability.

The delay line acts as an intermediary mechanism between the low-frequency system clock and the high-resolution timing requirement. By introducing this intermediate delay line clock domain, the system achieves high timing resolution without requiring the main system clock to run at high frequency, thereby avoiding the need for a fully high-frequency system implementation that would require larger die area.

The patent implements dynamic clock domain separation where the delay line clock operates at high frequency only during measurement intervals and is synchronized with the system clock. This dynamic operation reduces the window of opportunity for noise interference compared to continuous high-frequency operation, while still achieving high timing resolution during active measurements.

The delay line clock serves as an intermediary that translates low-frequency system clock signals into high-resolution timing measurements without requiring the entire system to operate at high frequency. This intermediary approach isolates the noise-sensitive high-frequency operations to a controlled domain, reducing overall noise sensitivity while maintaining measurement precision.