Semiconductor Delay-Line Timing Alignment Across Supply Voltages
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Solution Overview
Problem
In semiconductor apparatuses, timing skew and phase differences between data and clock signals can occur due to voltage level discrepancies between different supply voltages, affecting data synchronization and setup/hold times.
Innovation Solution
The semiconductor apparatus employs voltage detection circuits to generate delay control signals based on supply voltage levels, allowing the delay lines to adjust their delay amounts complementarily, ensuring synchronization between data and clock signals by varying the delay of the first and second delay lines based on the relative voltage levels of the first and second supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different supply voltages are used for data receiver and strobe receiver, then power supply flexibility is improved, but timing skew and phase differences occur between data and clock signals
Solution Approach 1:
The patent changes the delay parameters of delay lines based on supply voltage levels. Voltage detection circuits detect the first and second supply voltage levels, and based on these detected levels, the delay amounts of the first and second delay lines are adjusted to compensate for timing skew caused by voltage differences between data and strobe receivers.
2Device complexity
If delay amounts of delay lines are fixed, then device complexity is reduced, but timing skew cannot be compensated for under voltage level variations
Solution Approach 1:
The patent makes the delay lines dynamic by allowing their delay amounts to be adjusted based on detected supply voltage levels. The voltage detection circuits continuously monitor voltage levels, and the delay lines dynamically adjust their delay characteristics to maintain proper timing synchronization between data and strobe signals despite voltage variations.
3Reliability
If delay amounts are adjusted based on voltage detection, then timing synchronization is improved, but device complexity increases due to additional voltage detection circuits
Solution Approach 1:
The voltage detection circuits serve multiple functions: they detect supply voltage levels for timing skew compensation, and their outputs control both the first and second delay lines. This multi-functionality reduces the need for separate dedicated circuits for each delay line, thereby mitigating the increase in device complexity while maintaining improved timing synchronization.
Data Source
AI summary
A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages.