Process-Insensitive Delay Line With Stable Timing Control
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Solution Overview
Problem
Conventional delay lines in electronic devices are susceptible to significant variations in delay time due to process and environmental factors such as fabrication imperfections, temperature changes, and power supply fluctuations, leading to over-designing of circuits and devices to accommodate uncertainties, which can result in reduced performance and increased noise patterns.
Innovation Solution
A process-insensitive delay line is introduced, which uses a digitally controlled current source to adjust delay time through a ratio of charging and control currents, ensuring that the delay time remains consistent despite variations, by using a voltage-controlled delay unit and phase detector to maintain a stable delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay lines using series invertors are used to accommodate fabrication imperfections, then device reliability is improved, but delay time stability deteriorates due to process and environmental variations
Solution Approach 1:
The patent changes the controlling parameter from fixed invertor chains to digitally adjustable delay elements. The delay time is controlled by a digital code that selects from multiple predetermined delay values, making the delay time stable against process and environmental variations while maintaining reliability.
Solution Approach 2:
The patent introduces dynamic adjustability to the delay line through digital control. The delay time can be dynamically selected from multiple predetermined values based on operating conditions, allowing the system to adapt to process variations and maintain both reliability and stability.
2Reliability
If design margin is increased to accommodate delay time variations, then reliability is improved, but circuit performance deteriorates due to over-design
Solution Approach 1:
The patent changes the delay time parameter from a fixed conservative estimate to a precisely controllable value selected from multiple predetermined options. This eliminates the need for excessive design margins while ensuring reliable operation, thereby improving circuit performance without sacrificing reliability.
3Productivity
If delay time is reduced to meet timing requirements, then productivity is improved, but manufacturing precision deteriorates due to process variations
Solution Approach 1:
The patent segments the delay line into multiple discrete delay elements, each contributing a predetermined delay value. The total delay time is the sum of selected segment delays, allowing precise control of the total delay while compensating for process variations through digital selection.
Solution Approach 2:
The patent uses digital control to precisely set the delay time parameter from multiple predetermined values. This allows the delay time to be accurately controlled to meet timing requirements while compensating for manufacturing variations through digital adjustment.
Data Source
AI summary
A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.