Dual-Threshold Delay-Line Circuit for Voltage Droop Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern integrated circuits face voltage droop issues due to rapid changes in processor core activity, leading to transient power supply voltage drops, which existing mitigation techniques like lowering clock frequency can cause timing failures.
Innovation Solution
A circuit comprising first and second signal delay lines with different threshold voltages, a phase detector, reset circuit, and clock controller to detect voltage droop by adjusting clock frequency based on comparison signals, with calibration to ensure equal delays at target voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock frequency is lowered to mitigate voltage droop, then the voltage droop impact is reduced, but timing failures occur and performance decreases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment based on real-time voltage droop detection. The system continuously monitors voltage conditions and adjusts the clock frequency dynamically - lowering it only when voltage droop is detected and restoring it when voltage stabilizes. This dynamic approach prevents timing failures during droop events while maintaining high performance during normal operation, resolving the contradiction between reliability and productivity.
2Reliability
If the clock frequency is lowered to prevent timing failures, then timing reliability improves, but performance and throughput decrease
Solution Approach 1:
The patent employs a feedback mechanism where the system continuously monitors voltage droop conditions and adjusts clock frequency accordingly. When voltage droop is detected, the clock frequency is lowered to prevent timing failures; when voltage returns to normal, the frequency is restored. This closed-loop feedback control ensures timing reliability is maintained only when necessary, preserving throughput during normal operation while preventing timing errors during droop events.
Data Source
AI summary
A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.