Delay Lock Loop Feedback Selection for Faster Phase Locking
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Solution Overview
Problem
The existing delay lock loops in dynamic random access memory face challenges with increased frequency, leading to higher current consumption and longer lock times due to the need for additional delay in the delay line, which reduces working efficiency.
Innovation Solution
A delay lock loop and phase locking method that reduce the number of delay elements in the delay line by using a first divider, delay line, frequency multiplier, second divider, phase detection and controlling circuit, and setting signal generator to selectively choose a feedback clock signal closer in phase to the reference clock signal, thereby reducing the required delay value and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay line provides extra delay to accommodate frequency reduction control, then the locking mechanism works, but current consumption increases
Solution Approach 1:
The patent applies dynamics by making the delay line delay amount adjustable rather than fixed. The delay control signal dynamically adjusts the delay amount based on phase detection results, allowing the system to use minimal delay necessary for locking rather than providing extra fixed delay, thereby reducing current consumption while maintaining reliable locking
Solution Approach 2:
The patent changes the delay parameter of the delay line dynamically. By adjusting the delay amount according to phase detection feedback, the system optimizes the delay parameter to be just sufficient for locking rather than excessive, which reduces power consumption while ensuring the locking mechanism functions reliably
2Reliability
If the delay line provides extra delay to accommodate frequency reduction control, then the locking mechanism works, but lock time increases
Solution Approach 1:
The patent implements feedback by using phase detection to continuously monitor the phase difference between reference and feedback clock signals. This feedback enables the delay line to adjust its delay amount dynamically, converging quickly to the optimal locking point rather than relying on excessive fixed delay, thus reducing lock time while maintaining reliable locking
Solution Approach 2:
The system dynamically adjusts the delay line's delay amount based on real-time phase detection results. This dynamic adjustment allows the system to reach locking faster by progressively optimizing the delay rather than using a conservative extra delay setting, reducing lock time while ensuring reliable locking mechanism operation
3Reliability
If more delay elements are added to the delay line to provide extra delay, then the delay requirement is met, but device complexity increases
Solution Approach 1:
The patent makes the delay line dynamically adjustable, allowing a smaller number of delay elements to provide variable delay amounts rather than requiring many fixed delay elements. The delay control signal enables the same hardware to adapt delay to match requirements, reducing device complexity while meeting delay requirements through flexible control
Solution Approach 2:
The patent changes the delay parameter of existing delay elements through control signals rather than adding more physical elements. By adjusting the delay amount of each element dynamically, the system meets varying delay requirements with a compact number of reusable delay elements, reducing device complexity
Data Source
AI summary
A delay lock loop and a phase locking method thereof are provided. The delay lock loop includes a first divider, a delay line, a frequency multiplier, a second divider, a phase detection and controlling circuit and a setting signal generator. The first divider generates a divided reference clock signal. The second divider generates a first feedback clock signal and a second feedback clock signal which are complementary by dividing an output clock signal, and generates a selected feedback clock signal by selecting the first or second feedback clock signal according to a setting signal. The phase detection and controlling circuit compares phases of the selected feedback clock signal and the divided reference clock signal to generate a delay control signal. The setting signal generator samples the divided reference clock signal by the first feedback clock signal to generate the setting signal.