Delay Lock Loop Phase Control for Initial Delay Elimination
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Solution Overview
Problem
Integrated circuits (ICs) face issues with clock signal stability due to manufacturing processes and temperature variations, leading to normal operation failures.
Innovation Solution
A delay lock loop comprising a delay unit, an elimination unit, a phase detection unit, and a control unit, which adjusts the delay factor based on phase differences between clock signals to eliminate initial delays and ensure synchronization, using fewer components than conventional designs, thereby reducing consumption and increasing usable space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay lock loop designs are used, then clock signal synchronization can be achieved, but the device complexity and component count increase
Solution Approach 1:
The patent combines the delay unit and elimination unit into a unified structure where the elimination unit is integrated within the delay lock loop system. This merging reduces the overall component count while maintaining the functional separation needed for eliminating initial delay and achieving clock signal synchronization, thereby resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The delay unit is designed to serve multiple functions: it provides the necessary delay for synchronization while also being the target of elimination for initial delay. The control unit adjusts the delay factor to accomplish both synchronization and initial delay elimination, reducing the need for separate dedicated components and thus lowering device complexity while maintaining synchronization reliability.
2Reliability
If more components are used to eliminate initial delay, then clock signal stability improves, but the usable space decreases
Solution Approach 1:
By integrating the elimination unit within the existing delay lock loop structure and merging functional responsibilities, the patent reduces the total component count. This consolidation maintains clock signal stability through initial delay elimination while freeing up usable space in the integrated circuit, effectively resolving the contradiction between reliability and area.
3Reliability
If conventional delay lock loop designs are used, then clock signal synchronization can be achieved, but the power consumption increases
Solution Approach 1:
The patent merges the elimination unit with the delay lock loop structure, reducing the total number of active components. Fewer components result in lower overall power consumption while maintaining the synchronization function, thus resolving the contradiction between reliability and energy loss.
Solution Approach 2:
The control unit is designed to adjust the delay factor to accomplish multiple objectives: synchronization and initial delay elimination. This multi-functionality reduces the need for separate control mechanisms, lowering power consumption while maintaining synchronization reliability.
Data Source
AI summary
A delay lock loop is provided. A delay unit delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit generates an indication signal according to a phase difference between the second and fourth clock signals. When a duration of the indication signal being at a first level does not arrive at a pre-determined value and the indication signal is at a second level, the control unit increases the delay factor. When the duration of the indication signal being at the first level arrives at the pre-determined value and the indication signal is at the second level, the control unit reduces the delay factor.