Delay-Locked Clock Synthesizer for High-Resolution Phase Control
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Solution Overview
Problem
Existing clock generation systems face challenges in achieving high resolution phase delay without requiring complex phase multiplexers, particularly in integrated circuits, and struggle to efficiently control clock phase with high precision.
Innovation Solution
A delay clock synthesizer (DLCS) comprising a phase detector, summing circuit, and loop filter is used to generate an output clock with controlled phase offset, allowing for high resolution phase delay control by summing phase error and offset signals and filtering the result to adjust the delay, eliminating the need for a high complexity phase multiplexer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a clock multiplexer is used to generate a variable phase clock, then the desired phase can be achieved, but the device complexity increases significantly
Solution Approach 1:
The patent extracts the phase control function from the complex clock multiplexer and implements it through a simplified delay lock loop circuit. The DLL circuit generates multiple delayed clock signals and selects the appropriate phase through feedback control, eliminating the need for a high-complexity multiplexer while maintaining phase control capability.
Solution Approach 2:
The patent employs a delay lock loop with feedback mechanism to control clock phase. The phase detector compares the output clock phase with a reference, and the loop filter adjusts the delay cells accordingly to achieve the desired phase shift, providing automatic phase control without complex multiplexer logic.
2Measurement precision
If the number of delay stages is increased to achieve higher phase delay resolution, then the resolution improves, but the device complexity increases
Solution Approach 1:
The patent uses dynamically controllable delay cells within the DLL circuit, where each cell's delay can be adjusted through voltage control. This dynamic adjustment capability allows achieving fine phase resolution without proportionally increasing the number of delay stages, as the feedback mechanism optimizes the utilization of available delay elements.
Data Source
AI summary
A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.