Delay Locked Loop Circuit With Multiphase Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay locked loop circuits in semiconductor memory devices face challenges in high-speed operations due to long phase lock times, duty cycle ratio variations, and vulnerability to noise and jitter, especially when handling high-frequency system clocks.
Innovation Solution
A semiconductor memory device with a delay locked loop circuit that includes a phase comparator, phase adjuster, digital-to-analog converter, and multiphase delay signal generator, utilizing a finite state machine to detect phase differences and generate multiphase delay signals through a voltage-controlled delay line, allowing for digital phase adjustment and reduced phase lock time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the system clock frequency is increased to achieve higher data input/output speed, then the productivity is improved, but the phase lock time becomes longer and the circuit becomes more vulnerable to noise and jitter
Solution Approach 1:
The delay locked loop circuit is divided into multiple independent functional modules: phase detector, charge pump, loop filter, and delay line. Each module operates independently to detect phase differences, generate control signals, filter noise, and adjust delay respectively. This segmentation allows the circuit to maintain stability at high frequencies while reducing overall phase lock time by parallelizing the adjustment process across multiple stages.
Solution Approach 2:
The delay line employs dynamically adjustable delay elements whose delay amounts can be modified in real-time based on feedback from the phase detector. The circuit transitions from a static delay configuration to a dynamic one where delay parameters are continuously optimized during operation, enabling faster phase locking and adaptation to high-frequency clock signals without losing synchronization stability.
2Reliability
If the delay locked loop circuit uses conventional continuous adjustment method, then the phase synchronization is achieved, but the circuit becomes vulnerable to noise and jitter affecting stability
Solution Approach 1:
The phase detector operates periodically to sample phase differences at specific intervals rather than continuously. This periodic sampling approach reduces the circuit's sensitivity to high-frequency noise and jitter by only measuring phase relationships at stable points in the clock cycle, thereby maintaining reliable synchronization while filtering out harmful periodic disturbances.
Solution Approach 2:
The circuit implements a closed-loop feedback mechanism where the phase detector continuously monitors the phase relationship between input and output clocks, and the delay line adjusts its delay based on this feedback. This negative feedback system automatically corrects for noise and jitter by detecting deviations and making real-time compensatory adjustments, ensuring stable phase synchronization even in noisy environments.
3Measurement precision
If the delay locked loop circuit implements fine phase adjustment, then the synchronization precision is improved, but the device complexity increases
Solution Approach 1:
The delay line introduces an additional dimension of control by using multiple independently adjustable delay stages instead of a single complex continuous adjustment mechanism. Each stage can be controlled separately, providing fine-grained phase adjustment capability while maintaining a relatively simple overall circuit structure. This dimensional approach to delay control enables precise phase detection without proportionally increasing circuit complexity.
Data Source
AI summary
A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.