Delay-Locked Loop Chip Screening for Fast Speed Grading
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Solution Overview
Problem
Conventional methods for screening high-speed chips during mass production are time-consuming, incomplete, and unreliable, and require unnecessary equipment, such as oscilloscopes, due to limitations in built-in self-test loops and direct signal testing capabilities.
Innovation Solution
A voltage-controlled delay line (VCDL) integrated with automated testing equipment, which receives a reference clock signal, generates an output clock signal by adjusting a delay code based on phase error signals, and outputs the delay code to determine the maximum chip speed, enabling accurate and repeatable speed screening without additional instruments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a built-in self-test (BIST) loop is used to determine chip speed, then the chip speed can be measured, but the screening process becomes time-consuming due to frequency sweeping
Solution Approach 1:
The patent pre-configures a delay line with multiple fixed delay stages corresponding to different speed grades. Instead of sweeping through frequencies during testing, the system preliminarily establishes these delay stages during manufacturing, allowing direct measurement by comparing the chip's operating frequency against the pre-set delay stages, thus eliminating time-consuming frequency sweeping
Solution Approach 2:
The patent uses a voltage-controlled delay line where the delay amount can be dynamically adjusted by changing the control voltage. This dynamic adjustment allows the system to quickly switch between different delay stages without mechanical movement or complex reconfiguration, enabling fast comparison across multiple speed grades during screening
2Measurement precision
If a ring oscillator is used to measure chip speed, then the speed can be determined by frequency measurement, but an oscilloscope is required which is impractical for production testing
Solution Approach 1:
The patent extracts the frequency measurement function from external equipment (oscilloscope) and integrates it directly into the chip's on-board delay line. The delay line itself becomes the measurement instrument, eliminating the need for external oscilloscopes and simplifying the testing equipment required for production testing
Solution Approach 2:
The delay line structure serves multiple functions: it acts as both a signal processing element (delaying the clock signal) and a measurement instrument (providing reference delay stages for speed grading). This multi-functionality eliminates the need for separate measurement equipment and integrates the measurement capability directly into the chip structure
3Productivity
If automated testing equipment is used to test high speed signals, then productivity increases, but ATE cannot directly test high speed signals due to hardware limitations
Solution Approach 1:
The patent introduces an on-chip delay line as an intermediary between the high-speed chip signal and the ATE. The delay line converts the high-speed signal into a measurable form by comparing it against pre-configured delay stages, allowing the ATE to indirectly measure high-speed signals through its existing, slower measurement capabilities without requiring hardware upgrades
4Measurement precision
If a built-in self-test (BIST) loop is used for screening, then chip speed can be measured, but the test is incomplete as it cannot cover the entire chip
Solution Approach 1:
The delay line is designed to work with any clock signal generated by any functional block on the chip. By universally accepting clock signals from different chip modules and comparing them against the pre-configured delay stages, the system achieves comprehensive coverage of the entire chip's speed performance, not just isolated test blocks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The VCDL system reduces test time, enhances repeatability, and provides precise speed grading, allowing for efficient high-speed chip screening during mass production without the need for oscilloscopes or other complex testing instruments.
Implementation Method 1
The VCDL is configured to generate the output clock signal by applying the delay code stored in the register to the reference clock signal to delay the reference clock signal
Implementation Method 2
The phase detector is configured to compare the reference clock signal with the output clock signal to generate at the output of the phase detector a phase error signal representing a phase delay between the reference clock signal and the output clock signal
Implementation Method 3
The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value
Data Source
AI summary
A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.