Delay-Locked Clock Circuit With Cycle-Based Phase Correction
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits in semiconductor devices suffer from stuck failure due to changes in process, voltage, and temperature (PVT) conditions, which affect the delay amount of the delay replica modeler, leading to phase misalignment between the source and feedback clocks.
Innovation Solution
The proposed DLL circuit includes a common delay line that selectively delays the source clock by one or more unit delays, a clock cycle detector to generate delay control codes, and a delay amount controller to adjust the delay control codes based on phase comparisons, ensuring the delay amount is adjusted by one cycle of the source clock to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay amount of the delay replica modeler is adjusted to compensate for PVT changes, then the phase alignment between source and feedback clocks is improved, but the delay amount may exceed tolerance ranges causing stuck failure
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism where the delay control code is updated based on real-time phase comparison results. The delay amount controller dynamically modifies the delay control code by adding or subtracting one cycle of the source clock phase, allowing the system to adapt to PVT changes while preventing the delay amount from exceeding tolerance ranges that would cause stuck failure.
Solution Approach 2:
The patent employs a feedback mechanism where the phase comparison unit continuously compares the source clock phase with the feedback clock phase and generates comparison results that are fed back to the delay amount controller. This closed-loop feedback system enables automatic adjustment of the delay amount to maintain phase alignment while preventing stuck failure through controlled incremental changes.
2Measurement precision
If the delay control code is adjusted frequently to maintain phase alignment, then the phase synchronization is improved, but the system stability may deteriorate due to excessive adjustments
Solution Approach 1:
The patent applies partial action by adjusting the delay control code by only one cycle of the source clock phase at each adjustment step, rather than making large incremental changes. This conservative adjustment strategy maintains system stability while gradually achieving phase synchronization, preventing oscillations that would result from excessive adjustments.
3Measurement precision
If the delay amount is increased to compensate for large PVT variations, then the phase alignment is improved, but the risk of stuck failure increases
Solution Approach 1:
The patent implements preliminary action by detecting when the phase comparison result indicates an approaching tolerance limit and proactively adjusting the delay control code by one cycle before the delay amount exceeds the safe range. This preventive approach allows the system to compensate for PVT variations while maintaining a safety margin that prevents stuck failure.
Data Source
AI summary
A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.