Delay-Locked Pixel Control for Lower-Current TOF Imaging
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Solution Overview
Problem
Imaging systems with time-of-flight (TOF) sensing capabilities face challenges in managing high instantaneous current draw due to high-frequency charge modulation across the pixel array, straining the power delivery network, which can lead to unpredictable depth errors and require bulky power delivery networks.
Innovation Solution
Implementing an adjustable delay line with delay locking in the pixel control circuitry to stagger the modulation of pixel sets, reducing peak current draw and ensuring predictable timing delays through phase locking, thereby mitigating depth errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-frequency charge modulation is performed simultaneously across all pixels, then depth measurement capability is maintained, but peak current draw increases and strains the power delivery network
Solution Approach 1:
The pixel array is divided into multiple groups, and charge modulation is performed sequentially on different groups rather than simultaneously on all pixels. This segmentation of the pixel array allows the system to maintain depth measurement capability while reducing peak current draw by distributing the modulation current across multiple time slots.
Solution Approach 2:
Charge modulation is performed in periodic cycles, where different groups of pixels are modulated in successive time periods. This periodic action ensures that depth measurement data can still be collected across the full array while spreading the power demand over time, preventing excessive peak current draw.
2Power
If charge modulation is staggered across pixel sets to reduce peak current, then power delivery network is eased, but timing delays become unpredictable causing depth errors
Solution Approach 1:
A delay lock loop circuit is implemented that continuously monitors the actual timing delays introduced by the staggered modulation scheme and provides feedback to adjust the modulation timing. This feedback mechanism ensures that despite the sequential modulation of different pixel groups, the timing delays remain predictable and compensated, preventing depth measurement errors.
Solution Approach 2:
A delay lock loop circuit acts as an intermediary between the staggered charge modulation process and the depth measurement calculation. This intermediary component measures and compensates for the timing delays introduced by sequential modulation, ensuring that the final depth measurements remain accurate despite the staggered timing of different pixel groups.
3Reliability
If simultaneous charge modulation is performed across all pixels, then timing consistency is maintained, but bulky power delivery network is required
Solution Approach 1:
The pixel array is segmented into multiple groups that are modulated sequentially, which reduces the peak current requirements and allows for a more compact power delivery network. The segmentation maintains timing consistency within each group while distributing the overall power demand across multiple time slots.
Solution Approach 2:
The system employs periodic charge modulation across different pixel groups, where each group undergoes modulation in successive periods. This periodic approach reduces the instantaneous power requirements, enabling a smaller power delivery network while maintaining reliable depth measurements through the structured timing of modulation cycles.
Data Source
AI summary
An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.