Delay Locked Loop Clock Stabilization During Memory Read Operations
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Solution Overview
Problem
Conventional delay locked loops experience data loss or duplication due to periodic updates in delay values, leading to unstable data processing, especially during read operations in semiconductor memory devices.
Innovation Solution
A delay locked loop with a closed loop circuit generating preliminary delay information, a control unit updating this information into delay information only when necessary, and a first delay unit adjusting the input clock signal based on the updated delay information to stabilize the output clock signal, reducing power consumption and maintaining stability during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay locked loop periodically updates the delay value to compensate for skew, then the phase matching between internal and external clock signals is improved, but data loss or duplication occurs during read operations
Solution Approach 1:
The patent implements dynamic control of the delay value update mechanism. The delay locked loop continuously monitors phase differences and dynamically adjusts the delay value only when necessary, rather than using fixed periodic updates. This dynamic approach allows the system to maintain precise phase matching while avoiding updates during critical read operations, thereby preventing data loss or duplication.
Solution Approach 2:
The patent performs preliminary phase detection and delay adjustment before read operations begin. By detecting phase differences and adjusting delay values in advance during non-critical periods, the system ensures that the delay value is stable and accurate when read operations occur, preventing data processing issues while maintaining phase synchronization.
2Measurement precision
If the delay locked loop continuously updates the delay value to adapt to temperature variations, then the compensation accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic but conditional delay value updates rather than continuous updates. The system updates delay values at specific intervals or when triggered by detected phase differences, rather than continuously monitoring and adjusting. This periodic approach maintains compensation accuracy for temperature variations while significantly reducing power consumption compared to continuous update mechanisms.
Solution Approach 2:
The patent changes the operational parameters of the delay locked loop based on system state. The update frequency and sensitivity of phase detection are adjusted dynamically - using higher sensitivity and more frequent updates when temperature variations are detected, and reducing update frequency during stable conditions. This adaptive parameter change maintains compensation accuracy while optimizing power consumption.
Data Source
AI summary
A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.