Delay Locked Loop with Split Delay Paths for Stable Clock Switching
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Solution Overview
Problem
Conventional delay locked loops face challenges in maintaining stable operation across a wide range of external clock frequencies, leading to increased load on output lines and power consumption, particularly when switching between high and low frequencies, resulting in jitter and unstable data windows.
Innovation Solution
A delay locked loop design that separates output lines for high and low frequency operations, utilizing two cascade-connected variable delay units and a selecting circuit to maintain constant load on the output line, ensuring stable clock generation across frequency bands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single variable delay unit is used to cover both high and low frequency operations, then the delay locked loop can operate across a wide frequency range, but the load on the output line increases and becomes unstable when switching between frequency bands
Solution Approach 1:
The variable delay unit is divided into two separate units: a first variable delay unit for high frequency operations and a second variable delay unit for low frequency operations. Each unit has its own dedicated output line, which prevents load instability when switching between frequency bands. The selecting circuit chooses which delay unit's output to use based on the current frequency band, thereby maintaining stable output line load characteristics.
2Adaptability or versatility
If the delay locked loop is designed to tolerate both high and low frequency external clock signals, then it can generate locked internal clock signals across frequency bands, but power consumption increases due to the heavy load on the output line
Solution Approach 1:
By segmenting the delay functionality into two separate variable delay units with dedicated output lines, each unit operates with a manageable load appropriate for its frequency range. This eliminates the need for the output line to handle the heavy combined load of both high and low frequency operations simultaneously, thereby reducing overall power consumption while maintaining frequency bandwidth tolerance.
3Adaptability or versatility
If the output line load varies when switching between high and low frequency operations, then the delay locked loop can adapt to different frequency bands, but jitter occurs and data windows become unstable
Solution Approach 1:
The system segments the delay functionality into two separate variable delay units, each with its own dedicated output line. This segmentation ensures that when switching between frequency bands, the output line load remains stable because each line is dedicated to a specific frequency range. The selecting circuit smoothly transitions between the two delay units based on frequency detection, preventing load variations that would cause jitter and data window instability.
4Device complexity
If a single output line is used for both high and low frequency operations, then the device complexity is reduced, but the load on the output line becomes heavy and unstable
Solution Approach 1:
Instead of using a single output line for both frequency operations, the system segments the output into two separate dedicated lines: one for high frequency operations and one for low frequency operations. This segmentation, combined with a selecting circuit, maintains device complexity at an acceptable level while significantly improving output line load consistency. Each dedicated line handles only its designated frequency range, preventing load instability.
Data Source
AI summary
A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.