Asynchronous Delay Loop Self-Calibration Using Counter Feedback
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Solution Overview
Problem
Existing delay circuits in asynchronous loops, such as those used in analog-to-digital converters, are prone to errors due to noise and improper settling, which are exacerbated by process, voltage, and temperature variations, leading to unreliable clock signals and data transmission issues.
Innovation Solution
A self-calibrating delay generating circuit using digital counter feedback to monitor and adjust delays in an asynchronous loop, allowing for calibration without disrupting the underlying circuit operation, by enabling a number of unit delay elements based on a multibit output of a counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay circuits are used in asynchronous loops for clock signal generation, then clock signals can be generated internally without external clock inputs, but the circuits are prone to errors due to noise and improper settling under process, voltage, and temperature variations
Solution Approach 1:
The patent implements a feedback mechanism where a counter counts the number of clock cycles generated by the delay loop, and this count is fed back to adjust the delay circuit parameters. The system compares the actual clock cycle count against expected values and dynamically adjusts the delay elements to compensate for drift caused by PVT variations, thereby maintaining reliable clock signal generation
Solution Approach 2:
The delay circuit performs self-calibration by using its own generated clock signal to drive a counter, which then provides feedback for automatic adjustment. The system serves itself by monitoring its own performance and making corrections without external intervention, adapting to changing conditions automatically
2Reliability
If calibration circuits are added to adjust delay parameters, then clock signal accuracy can be improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent adjusts delay parameters by changing the effective delay element values based on counter feedback. The system modifies delay circuit parameters dynamically by enabling or disabling specific delay elements in response to calibration data, allowing accurate clock generation without complex additional calibration hardware
Solution Approach 2:
The patent uses a simplified replica or model of the delay loop behavior through the counter circuit to determine calibration requirements. The counter provides a digital representation of the clock signal characteristics, which is then used to adjust the actual delay circuit, avoiding the need for complex direct measurement and calibration mechanisms
3Manufacturing precision
If delay elements are adjusted to compensate for process, voltage, and temperature variations, then timing accuracy can be maintained, but the adjustment mechanism adds device complexity
Solution Approach 1:
The delay circuit is divided into multiple discrete delay elements that can be individually enabled or disabled. This segmentation allows fine-grained adjustment of the total delay by selectively activating specific elements based on calibration requirements, achieving precise timing control through simple binary selection of pre-designed delay units
Data Source
AI summary
A calibration circuit has a delay loop, a counter and a latch. The delay loop that includes a delay circuit. The counter is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state. The latch is configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state. A number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter. In one example, the number of enabled unit delay elements is based on a difference between the multibit output of the counter and a multibit value expected to be generated when the delay circuit is operating nominally.