Delay Locked Loop with Shared Delay Line for Four-Phase Clocks
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Solution Overview
Problem
The existing delay locked loops in semiconductor memory, such as DRAM, require multiple variable delay lines to synchronize and lock four-phase clock signals, leading to increased manufacturing costs and high power consumption.
Innovation Solution
A delay locked loop with a pre-processing module, a first variable delay line, and a phase processing module, where the pre-processing module receives an initial clock signal and outputs a first clock signal, and the phase processing module adjusts the first target clock signal using a preset control code to generate a set of target clock signals with a preset phase difference, reducing the number of variable delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple variable delay lines are used to synchronize four-phase clock signals, then phase synchronization is achieved, but circuit area and power consumption increase
Solution Approach 1:
The patent merges multiple variable delay lines into a single shared variable delay line that serves all four-phase clock signals. Instead of having separate delay lines for each phase, one variable delay line is used to adjust the phase of clock signals across all phases, reducing circuit area while maintaining synchronization capability
Solution Approach 2:
The single variable delay line is designed to perform multiple functions: it adjusts phase for multiple clock phases simultaneously and works in conjunction with the phase processing module to generate the required four-phase clock signals with precise phase relationships, replacing what would traditionally require multiple specialized delay lines
2Reliability
If multiple variable delay lines are used to synchronize four-phase clock signals, then phase synchronization is achieved, but power consumption increases
Solution Approach 1:
By combining multiple variable delay lines into one shared resource, the patent reduces the total number of active circuits that consume power. The single variable delay line and phase processing module together perform the work of multiple separate delay lines, resulting in lower overall power consumption while achieving the same phase synchronization function
3Manufacturing precision
If at least four main variable delay lines are set in the delay locked loop, then calibration of four-phase clock signals is realized, but manufacturing cost increases
Solution Approach 1:
The patent reduces the component count by merging multiple variable delay lines into a single shared delay line combined with a phase processing module. This simplification directly lowers manufacturing cost by reducing the number of individual components that need to be fabricated, assembled, and tested, while the phase processing module ensures calibration precision is maintained
Data Source
AI summary
A delay locked loop is provide, including a pre-processing module, a first variable delay line and a phase processing module. The pre-processing module is configured to receive an initial clock signal, pre-process the initial clock signal and output a first clock signal. The first variable delay line is configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal. The phase processing module is configured to receive a preset control code and the first target clock signal, perform delay processing on the first target clock signal based on the preset control code, and output at least one delayed target clock signal.