Delay-Locked Loop with Sequential Code Updates for Phase Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay locked loops in semiconductor devices face limitations in operating frequency due to minimum delay constraints and degrade in time resolution, leading to phase misalignment and performance issues.
Innovation Solution
A delay locked loop design that includes a main delay circuit with unit delay lines and a sub-delay circuit, where delay amounts are adjusted via code signals, allowing for sequential updating of code signals to maintain optimal time resolution and phase alignment, thereby improving the quality of multi-phase clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the delay locked loop uses a minimum delay to generate multiple phase clocks, then the phase difference between clocks is maintained, but the operating frequency is limited
Solution Approach 1:
The delay locked loop is divided into multiple independent unit delay lines (first, second, third, and fourth unit delay lines), each capable of independent delay adjustment. This segmentation allows each unit to contribute to the overall phase generation without being constrained by a single minimum delay value, enabling higher operating frequencies while maintaining precise phase alignment through individual code signal control.
2Measurement precision
If all unit delay lines are updated simultaneously, then the phase alignment is maintained, but the time resolution increases and performance degrades
Solution Approach 1:
The code signals for the unit delay lines are updated in a periodic sequential manner rather than simultaneously. The digital circuit updates each code signal (first, second, third, fourth code signals) in sequence based on phase detection results, creating a periodic update pattern that maintains time resolution while ensuring phase alignment through iterative adjustment.
3Measurement precision
If the delay locked loop generates four phase clocks with minimum delay, then the phase difference corresponds to 90°, but the total time resolution increases to 4*TRES
Solution Approach 1:
The four unit delay lines are segmented and controlled independently with separate code signals. This allows the phase detection and adjustment process to work on individual segments sequentially, maintaining fine time resolution (TRES) for each segment while achieving overall phase alignment, avoiding the degradation to 4*TRES that would occur with simultaneous updates.
Solution Approach 2:
The phase detector continuously monitors the phase difference between phase clocks and provides feedback to the digital circuit. This feedback mechanism enables iterative adjustment of code signals for each unit delay line, ensuring precise phase alignment is achieved through continuous correction rather than bulk adjustment, thereby maintaining high time resolution.
Data Source
AI summary
A delay locked loop includes a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals; a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks; a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; and a digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit.